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    Dual layer patterning scheme to make dual damascene
    1.
    发明授权
    Dual layer patterning scheme to make dual damascene 失效
    双层图案方案制作双镶嵌

    公开(公告)号：US07078348B1

    公开(公告)日：2006-07-18

    申请号：US09893188

    申请日：2001-06-27

    申请人： Bhanwar Singh ,  Ramkumar Subramanian ,  Bharath Rangarajan ,  Michael K. Templeton

    发明人： Bhanwar Singh ,  Ramkumar Subramanian ,  Bharath Rangarajan ,  Michael K. Templeton

    IPC分类号： H01L21/302 ,  H01L21/3065

    CPC分类号： H01L21/31144 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813

    摘要： One aspect of the present invention relates to a method for making a dual damascene pattern in an insulative layer in a single etch process involving providing a wafer having at least one insulative layer formed thereon; depositing a first photoresist layer over the at least one insulative layer; patterning a first image into the first photoresist layer; curing the first patterned photoresist layer; depositing a second photoresist layer over the first patterned photoresist layer; patterning a second image into the second photoresist layer; and etching the at least one insulative layer through the first patterned photoresist layer and the second patterned photoresist layer simultaneously in the single etch process.

    摘要翻译： 本发明的一个方面涉及在单一蚀刻工艺中在绝缘层中制造双镶嵌图案的方法，该方法包括提供其上形成有至少一个绝缘层的晶片; 在所述至少一个绝缘层上沉积第一光致抗蚀剂层; 将第一图像图案化成第一光致抗蚀剂层; 固化第一图案化光致抗蚀剂层; 在所述第一图案化光致抗蚀剂层上沉积第二光致抗蚀剂层; 将第二图像图案化成第二光致抗蚀剂层; 以及在单次蚀刻工艺中同时蚀刻通过第一图案化光致抗蚀剂层和第二图案化光致抗蚀剂层的至少一个绝缘层。

    Active control of developer time and temperature
    2.
    发明授权
    Active control of developer time and temperature 失效
    主动控制显影时间和温度

    公开(公告)号：US06629786B1

    公开(公告)日：2003-10-07

    申请号：US09845232

    申请日：2001-04-30

    申请人： Bharath Rangarajan ,  Michael K. Templeton ,  Bhanwar Singh ,  Ramkumar Subramanian

    发明人： Bharath Rangarajan ,  Michael K. Templeton ,  Bhanwar Singh ,  Ramkumar Subramanian

    IPC分类号： G03D500

    CPC分类号： G03D5/00

    摘要： A system for regulating the time and temperature of a development process is provided. The system includes one or more light sources, each light source directing light to one or more gratings being developed on a wafer. Light reflected from the gratings is collected by a measuring system, which processes the collected light. Light passing through the gratings may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the progress of development of the respective portions of the wafer. The measuring system provides progress of development related data to a processor that determines the progress of development of the respective portions of the wafer. The system also includes a plurality of heating devices, each heating device corresponds to a respective portion of the developer and provides for the heating thereof. The processor selectively controls the heating devices so as to regulate temperature of the respective portions of the wafer.

    摘要翻译： 提供了一种用于调节开发过程的时间和温度的系统。 该系统包括一个或多个光源，每个光源将光引导到在晶片上显影的一个或多个光栅。 从光栅反射的光被测量系统收集，该系统处理收集的光。 通过光栅的光可以类似地由处理所收集的光的测量系统收集。 所收集的光表示晶片的各个部分的显影进展。 该测量系统提供开发相关数据的进展到处理器，该处理器确定晶片的相应部分的开发进度。 该系统还包括多个加热装置，每个加热装置对应于显影剂的相应部分并提供其加热。 处理器选择性地控制加热装置，以调节晶片各部分的温度。

    Use of RTA furnace for photoresist baking
    4.
    发明授权
    Use of RTA furnace for photoresist baking 有权
    使用RTA炉进行光刻胶烘烤

    公开(公告)号：US06335152B1

    公开(公告)日：2002-01-01

    申请号：US09564408

    申请日：2000-05-01

    申请人： Ramkumar Subramanian ,  Bharath Rangarajan ,  Michael K. Templeton ,  Bhanwar Singh

    发明人： Ramkumar Subramanian ,  Bharath Rangarajan ,  Michael K. Templeton ,  Bhanwar Singh

    IPC分类号： G03F738

    CPC分类号： G03F7/38

    摘要： In one embodiment, the present invention relates to a method of processing an irradiated photoresist involving the steps of placing a substrate having the irradiated photoresist thereon at a first temperature in a rapid thermal anneal furnace; heating the substrate having the irradiated photoresist thereon to a second temperature within about 0.1 seconds to about 10 seconds; cooling the substrate having the irradiated photoresist thereon to a third temperature in a rapid thermal annealing furnace within about 0.1 seconds to about 10 seconds; and developing the irradiated photoresist, wherein the second temperature is higher than the first temperature and the third temperature. In another embodiment, the present invention relates to a system of processing a photoresist, containing a source of actinic radiation and a mask for selectively irradiating a photoresist; a rapid thermal annealing furnace for rapidly heating and rapidly cooling a selectively irradiated photoresist, wherein the rapid heating and rapid cooling are independently conducted within about 0.1 seconds to about 10 seconds; and a developer for developing a rapid thermal annealing furnace heated and selectively irradiated photoresist into a patterned photoresist.

    摘要翻译： 在一个实施方案中，本发明涉及一种处理被照射的光致抗蚀剂的方法，包括以下步骤：在快速热退火炉中将具有照射光致抗蚀剂的基底在第一温度下放置; 将其上具有照射的光致抗蚀剂的基板加热至约0.1秒至约10秒的第二温度; 将快速热退火炉中具有照射光致抗蚀剂的基板冷却至约0.1秒至约10秒的第三温度; 并且显影所述被照射的光致抗蚀剂，其中所述第二温度高于所述第一温度和所述第三温度。 在另一个实施方案中，本发明涉及一种处理含有光化辐射源的光致抗蚀剂的系统和用于选择性地照射光致抗蚀剂的掩模; 快速热退火炉，用于快速加热和快速冷却选择性照射的光致抗蚀剂，其中快速加热和快速冷却在约0.1秒至约10秒内独立进行; 以及用于将快速热退火炉加热并选择性地照射光致抗蚀剂的显影剂加工成图案化的光致抗蚀剂。

    System and method for in situ control of post exposure bake time and temperature
    6.
    发明授权
    System and method for in situ control of post exposure bake time and temperature 失效
    曝晒后烘烤时间和温度的现场控制系统和方法

    公开(公告)号：US06641963B1

    公开(公告)日：2003-11-04

    申请号：US09845239

    申请日：2001-04-30

    申请人： Bharath Rangarajan ,  Michael K. Templeton ,  Bhanwar Singh ,  Ramkumar Subramanian

    发明人： Bharath Rangarajan ,  Michael K. Templeton ,  Bhanwar Singh ,  Ramkumar Subramanian

    IPC分类号： G03F900

    CPC分类号： G03F7/38 ,  G03B27/52

    摘要： A system for regulating temperature of a post exposure baking process is provided. The system includes one or more light sources, each light source directing light to one or more gratings being baked and hardened on a wafer. Light reflected from the gratings is collected by a measuring system, which processes the collected light. Light passing through the gratings may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the baking and hardening of the respective portions of the wafer. The measuring system provides baking and hardening related data to a processor that determines the baking and hardening of the respective portions of the wafer. The system also includes a plurality of temperature controlling devices, each such device corresponds to a respective portion of the wafer and provides for the heating and/or cooling thereof. The processor selectively controls the temperature controlling devices so as to regulate temperature of the respective portions of the wafer.

    摘要翻译： 提供了一种用于调节后曝光烘烤处理温度的系统。 该系统包括一个或多个光源，每个光源将光引导到在晶片上被烘烤和硬化的一个或多个光栅。 从光栅反射的光被测量系统收集，该系统处理收集的光。 通过光栅的光可以类似地由处理所收集的光的测量系统收集。 所收集的光表示晶片的各个部分的烘烤和硬化。 测量系统向处理器提供烘烤和硬化相关数据，该处理器确定晶片的相应部分的烘烤和硬化。 该系统还包括多个温度控制装置，每个这样的装置对应于晶片的相应部分并提供其加热和/或冷却。 处理器选择性地控制温度控制装置，以调节晶片各部分的温度。

    Use of scatterometry for in-situ control of gaseous phase chemical trim process
    7.
    发明授权
    Use of scatterometry for in-situ control of gaseous phase chemical trim process 有权
    使用散射法进行气相化学修饰过程的原位控制

    公开(公告)号：US06630361B1

    公开(公告)日：2003-10-07

    申请号：US09894701

    申请日：2001-06-28

    申请人： Bhanwar Singh ,  Bharath Rangarajan ,  Michael K. Templeton ,  Ramkumar Subramanian ,  Cristina Cheung

    发明人： Bhanwar Singh ,  Bharath Rangarajan ,  Michael K. Templeton ,  Ramkumar Subramanian ,  Cristina Cheung

    IPC分类号： H01L2100

    CPC分类号： H01L22/20 ,  G01N21/47 ,  G01N21/9501 ,  G01N21/956 ,  H01L21/67253

    摘要： A system for regulating a gaseous phase chemical trim process is provided. The system includes one or more light sources, each light source directing light to one or more features and/or gratings on a wafer. Light reflected from the features and/or gratings is collected by a measuring system, which processes the collected light. The collected light is indicative of the dimensions achieved at respective portions of the wafer. The measuring system provides trimming related data to a processor that determines the acceptability of the trimming of the respective portions of the wafer. The system also includes one or more trimming devices, each such device corresponding to a portion of the wafer and providing for the trimming thereof. The processor selectively controls the trimming devices to regulate trimming of the portions of the wafer.

    摘要翻译： 提供了一种用于调节气相化学修饰过程的系统。 该系统包括一个或多个光源，每个光源将光引导到晶片上的一个或多个特征和/或光栅。 从特征和/或光栅反射的光由测量系统收集，该系统处理收集的光。 所收集的光指示在晶片的相应部分处获得的尺寸。 测量系统向处理器提供修剪相关数据，该处理器确定了晶片各部分的修整的可接受性。 该系统还包括一个或多个修整装置，每个这样的装置对应于晶片的一部分并提供其修剪。 处理器选择性地控制修整装置来调节对晶片的部分的修整。

    Grainless material for calibration sample
    9.
    发明授权
    Grainless material for calibration sample 失效
    用于校准样品的粗糙材料

    公开(公告)号：US06459482B1

    公开(公告)日：2002-10-01

    申请号：US09729294

    申请日：2000-12-04

    申请人： Bhanwar Singh ,  Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Michael K. Templeton ,  Sanjay K. Yedur ,  Bryan K. Choo

    发明人： Bhanwar Singh ,  Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Michael K. Templeton ,  Sanjay K. Yedur ,  Bryan K. Choo

    IPC分类号： G01J110

    CPC分类号： H01J37/28 ,  H01J2237/2826

    摘要： The present invention provides SEM systems, SEM calibration standards, and SEM calibration methods that improved accuracy in critical dimension measurements. The calibration standards have features formed with an amorphous material such as amorphous silicon. Amorphous materials lack the crystal grain structure of materials such as polysilicon and are capable of providing sharper edged features and higher accuracy patterns than grained materials. The amorphous material can be bound to a silicon wafer substrate through an intermediate layer of material, such as silicon dioxide. Where the intermediate layer is insulating material, as is silicon dioxide, the intermediate layer may be patterned with gaps to provide for electrical communication between the amorphous silicon and the silicon wafer. Charges imparted to the amorphous silicon during electron beam scanning may thereby drain to the silicon wafer rather than accumulating to a level where they would distort the electron beam.

    摘要翻译： 本发明提供SEM系统，SEM校准标准和SEM校准方法，提高了临界尺寸测量的精度。 校准标准品具有非晶体材料如非晶硅形成的特征。 无定形材料缺乏诸如多晶硅的材料的晶粒结构，并且能够提供比颗粒材料更尖锐的边缘特征和更高精度的图案。 非晶材料可以通过诸如二氧化硅的材料的中间层与硅晶片衬底结合。 在中间层是绝缘材料的情况下，如二氧化硅那样，中间层可以用间隙图案化以提供非晶硅和硅晶片之间的电连通。 因此，在电子束扫描期间赋予非晶硅的电荷可以从而被排出到硅晶片，而不是积聚到它们会使电子束变形的水平。

    Deliberate void in innerlayer dielectric gapfill to reduce dielectric constant
    10.
    发明授权
    Deliberate void in innerlayer dielectric gapfill to reduce dielectric constant 有权
    内层介质间隙填料中的有意的空隙以降低介电常数

    公开(公告)号：US06445072B1

    公开(公告)日：2002-09-03

    申请号：US09617158

    申请日：2000-07-17

    申请人： Ramkumar Subramanian ,  Bhanwar Singh ,  Michael K. Templeton ,  Bharath Rangarajan

    发明人： Ramkumar Subramanian ,  Bhanwar Singh ,  Michael K. Templeton ,  Bharath Rangarajan

    IPC分类号： H01L214763

    CPC分类号： H01L21/7682 ,  Y10S977/897

    摘要： One aspect of the present invention relates to a method of forming an innerlayer dielectric, involving the steps of providing a substrate having at least two metal lines thereon; providing a conformal insulation layer over the substrate and metal lines; forming a second insulation layer over the conformal insulation layer, the second insulation layer containing a void positioned between two metal lines; at least one of thinning and planarizing the second insulation layer; and forming a third insulation layer over the second insulation layer. Another aspect of the present invention relates to an innerlayer dielectric semiconductor structure, containing a semiconductor substrate having at least two metal lines thereon; a conformal insulation layer over the semiconductor substrate and metal lines, the conformal insulation layer having a substantially uniform thickness from about 250 Å to about 5,000 Å; a second insulation layer over the conformal insulation layer, the second insulation layer containing a void positioned between two metal lines; and a third insulation layer over the second insulation layer.

    摘要翻译： 本发明的一个方面涉及一种形成内层电介质的方法，包括以下步骤：提供其上具有至少两条金属线的基底; 在衬底和金属线上提供保形绝缘层; 在所述保形绝缘层上形成第二绝缘层，所述第二绝缘层包含位于两条金属线之间的空隙; 将所述第二绝缘层变薄和平坦化的至少一个; 以及在所述第二绝缘层上形成第三绝缘层。 本发明的另一方面涉及一种内层电介质半导体结构，其包含其上具有至少两条金属线的半导体衬底; 半导体衬底和金属线上的共形绝缘层，保形绝缘层具有从大约至大约等于的大致均匀的厚度; 在保形绝缘层之上的第二绝缘层，所述第二绝缘层包含位于两个金属线之间的空隙; 以及在所述第二绝缘层上的第三绝缘层。