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公开(公告)号：US20090063818A1
公开(公告)日：2009-03-05
申请号：US11850410
申请日：2007-09-05
IPC分类号： G06F9/40
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3814 , G06F12/0859
摘要： A method of obtaining data, comprising at least one sector, for use by at least a first thread wherein each processor cycle is allocated to at least one thread, includes the steps of: requesting data for at least a first thread; upon receipt of at least a first sector of the data, determining whether the at least first sector is aligned with the at least first thread, wherein a given sector is aligned with a given thread when a processor cycle in which the given sector will be written is allocated to the given thread; responsive to a determination that the at least first sector is aligned with the at least first thread, bypassing the at least first sector, wherein bypassing a sector comprises reading the sector while it is being written; and responsive to a determination that the at least first sector is not aligned with the at least first thread, delaying the writing of the at least first sector until the occurrence of a processor cycle allocated to the at least first thread by retaining the at least first sector in at least one alignment register, thereby permitting the at least first sector to be bypassed.
摘要翻译： 一种获得数据的方法，包括至少一个扇区，供至少第一线程使用，其中每个处理器周期被分配给至少一个线程，包括以下步骤：请求至少第一线程的数据; 在接收到所述数据的至少第一扇区时，确定所述至少第一扇区是否与所述至少第一线程对准，其中当给定扇区将被写入的处理器周期时，给定扇区与给定线程对准 被分配给给定的线程; 响应于确定所述至少第一扇区与所述至少第一线程对准，绕过所述至少第一扇区，其中旁路扇区包括在被写入时读取扇区; 并且响应于确定所述至少第一扇区不与所述至少第一线程对准，延迟所述至少第一扇区的写入，直到通过保留所述至少第一线程来分配给所述至少第一线程的处理器周期的发生 在至少一个对准寄存器中的扇区，从而允许所述至少第一扇区被旁路。
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公开(公告)号：US07725659B2
公开(公告)日：2010-05-25
申请号：US11850410
申请日：2007-09-05
IPC分类号： G06F12/00
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3814 , G06F12/0859
摘要： A method of obtaining data, comprising at least one sector, for use by at least a first thread wherein each processor cycle is allocated to at least one thread, includes the steps of: requesting data for at least a first thread; upon receipt of at least a first sector of the data, determining whether the at least first sector is aligned with the at least first thread, wherein a given sector is aligned with a given thread when a processor cycle in which the given sector will be written is allocated to the given thread; responsive to a determination that the at least first sector is aligned with the at least first thread, bypassing the at least first sector, wherein bypassing a sector comprises reading the sector while it is being written; and responsive to a determination that the at least first sector is not aligned with the at least first thread, delaying the writing of the at least first sector until the occurrence of a processor cycle allocated to the at least first thread by retaining the at least first sector in at least one alignment register, thereby permitting the at least first sector to be bypassed.
摘要翻译： 一种获得数据的方法，包括至少一个扇区，供至少第一线程使用，其中每个处理器周期被分配给至少一个线程，包括以下步骤：请求至少第一线程的数据; 在接收到所述数据的至少第一扇区时，确定所述至少第一扇区是否与所述至少第一线程对准，其中当给定扇区将被写入的处理器周期时，给定扇区与给定线程对准 被分配给给定的线程; 响应于确定所述至少第一扇区与所述至少第一线程对准，绕过所述至少第一扇区，其中旁路扇区包括在被写入时读取扇区; 并且响应于确定所述至少第一扇区不与所述至少第一线程对准，延迟所述至少第一扇区的写入，直到通过保留所述至少第一线程来分配给所述至少第一线程的处理器周期的发生 在至少一个对准寄存器中的扇区，从而允许所述至少第一扇区被旁路。
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3.发明授权Method and apparatus for detecting clock gating opportunities in a pipelined electronic circuit design 有权用于检测流水线电子电路设计中的时钟门控机会的方法和装置公开(公告)号：US08073669B2
公开(公告)日：2011-12-06
申请号：US11842491
申请日：2007-08-21
IPC分类号： G06F17/50
CPC分类号： G06F1/3203 , G06F1/3237 , G06F9/3867 , Y02D10/128
摘要： A pipeline electronic circuit and design methodology enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit to achieve power conservation by incorporating clock-gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies.
摘要翻译： 管道电子电路和设计方法通过模拟来识别流水线各阶段之间的时钟门控机会，从而在管线的阶段实现功率节省。 在一个实施例中，模拟结果帮助设计者设计流水线电子电路，以通过在模拟识别的时钟选通机会位置处在流水线的各个阶段之间并入时钟选通电路来实现功率守恒。
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公开(公告)号：US20090249349A1
公开(公告)日：2009-10-01
申请号：US12059576
申请日：2008-03-31
申请人： Pradip Bose , Alper Buyuktosunoglu , Richard James Eickemeyer , Susan Elizabeth Eisen , Michael Stephen Floyd , Hans Mikael Jacobson , Jeffrey R. Summers
发明人： Pradip Bose , Alper Buyuktosunoglu , Richard James Eickemeyer , Susan Elizabeth Eisen , Michael Stephen Floyd , Hans Mikael Jacobson , Jeffrey R. Summers
IPC分类号： G06F9/46
CPC分类号： G06F9/4893 , Y02D10/24
摘要： A mechanism for controlling instruction fetch and dispatch thread priority settings in a thread switch control register for reducing the occurrence of balance flushes and dispatch flushes for increased power performance of a simultaneous multi-threading data processing system. To achieve a target power efficiency mode of a processor, the illustrative embodiments receive an instruction or command from a higher-level system control to set a current power consumption of the processor. The illustrative embodiments determine a target power efficiency mode for the processor. Once the target power mode is determined, the illustrative embodiments update thread priority settings in a thread switch control register for an executing thread to control balance flush speculation and dispatch flush speculation to achieve the target power efficiency mode.
摘要翻译： 一种用于控制在线程切换控制寄存器中的指令获取和调度线程优先级设置的机制，用于减少平衡刷新的发生和调度刷新以提高同时多线程数据处理系统的功率性能。 为了实现处理器的目标功率效率模式，说明性实施例从较高级系统控制器接收指令或命令以设置处理器的当前功耗。 说明性实施例确定了处理器的目标功率效率模式。 一旦确定了目标功率模式，则说明性实施例更新用于执行线程的线程切换控制寄存器中的线程优先级设置，以控制平衡冲突推测和调度冲销推测以实现目标功率效率模式。
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5.发明申请Structure For Detecting Clock Gating Opportunities In A Pipelined Electronic Circuit Design 有权用于检测流水线电子电路设计中的时钟门控机制的结构公开(公告)号：US20090217068A1
公开(公告)日：2009-08-27
申请号：US12347968
申请日：2008-12-31
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3237 , G06F9/3869 , G06F17/505 , G06F2217/78 , Y02D10/128
摘要： A design structure for a pipeline electronic processor device may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may embody a pipeline electronic circuit that enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit design structure to achieve power conservation by incorporating clock-gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies.
摘要翻译： 用于管道电子处理器设备的设计结构可以体现在用于设计，制造或测试处理器集成电路的机器可读介质中。 该设计结构可以体现管道电子电路，该管道电子电路能够通过模拟来识别流水线阶段之间的时钟选通机会，从而在管线的阶段中实现功率节省。 在一个实施例中，仿真结果帮助设计者设计流水线电子电路设计结构，以通过在模拟识别的时钟选通机会位置处在管线的阶段之间并入时钟选通电路来实现功率节省。
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6.发明授权Systems and methods for mutually exclusive activation of microprocessor resources to control maximum power 失效用于互相激活微处理器资源以控制最大功率的系统和方法公开(公告)号：US07447923B2
公开(公告)日：2008-11-04
申请号：US11207333
申请日：2005-08-19
申请人： Pradip Bose , Alper Buyuktosunoglu , Zhigang Hu , Hans Mikael Jacobson , Vijayalakshmi Srinivasan , Victor Zyuban
发明人： Pradip Bose , Alper Buyuktosunoglu , Zhigang Hu , Hans Mikael Jacobson , Vijayalakshmi Srinivasan , Victor Zyuban
CPC分类号： G06F1/3203 , G06F1/3287 , G06F1/329 , G06F9/30145 , G06F9/382 , G06F9/3836 , G06F9/3842 , G06F9/3867 , Y02D10/171 , Y02D10/24
摘要： A device for controlling power parameters in a microprocessor includes a resource activation control unit for controlling the maximum power of the microprocessor and two or more resources. The resource activation control unit controls the activation of the resources such that the consumed and dissipated power of the microprocessor does not exceed a power bound which is configurable to a predetermined value below the maximum power.
摘要翻译： 用于控制微处理器中的功率参数的装置包括用于控制微处理器的最大功率和两个或更多个资源的资源激活控制单元。 资源激活控制单元控制资源的激活，使得微处理器的消耗和耗散功率不超过可配置为低于最大功率的预定值的功率限制。
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公开(公告)号：US08261276B2
公开(公告)日：2012-09-04
申请号：US12059576
申请日：2008-03-31
申请人： Pradip Bose , Alper Buyuktosunoglu , Richard James Eickemeyer , Susan Elizabeth Eisen , Michael Stephen Floyd , Hans Mikael Jacobson , Jeffrey R. Summers
发明人： Pradip Bose , Alper Buyuktosunoglu , Richard James Eickemeyer , Susan Elizabeth Eisen , Michael Stephen Floyd , Hans Mikael Jacobson , Jeffrey R. Summers
CPC分类号： G06F9/4893 , Y02D10/24
摘要： A mechanism for controlling instruction fetch and dispatch thread priority settings in a thread switch control register for reducing the occurrence of balance flushes and dispatch flushes for increased power performance of a simultaneous multi-threading data processing system. To achieve a target power efficiency mode of a processor, the illustrative embodiments receive an instruction or command from a higher-level system control to set a current power consumption of the processor. The illustrative embodiments determine a target power efficiency mode for the processor. Once the target power mode is determined, the illustrative embodiments update thread priority settings in a thread switch control register for an executing thread to control balance flush speculation and dispatch flush speculation to achieve the target power efficiency mode.
摘要翻译： 一种用于控制在线程切换控制寄存器中的指令获取和调度线程优先级设置的机制，用于减少平衡刷新的发生和调度刷新以提高同时多线程数据处理系统的功率性能。 为了实现处理器的目标功率效率模式，说明性实施例从较高级系统控制器接收指令或命令以设置处理器的当前功耗。 说明性实施例确定了处理器的目标功率效率模式。 一旦确定了目标功率模式，则说明性实施例更新用于执行线程的线程切换控制寄存器中的线程优先级设置，以控制平衡冲突推测和调度冲销推测以实现目标功率效率模式。
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8.发明授权Structure for detecting clock gating opportunities in a pipelined electronic circuit design 有权用于在流水线电路设计中检测时钟门控机会的结构公开(公告)号：US08244515B2
公开(公告)日：2012-08-14
申请号：US12347968
申请日：2008-12-31
IPC分类号： G06F17/50
CPC分类号： G06F1/3203 , G06F1/3237 , G06F9/3869 , G06F17/505 , G06F2217/78 , Y02D10/128
摘要： A design structure for a pipeline electronic processor device may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may embody a pipeline electronic circuit that enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit design structure to achieve power conservation by incorporating clock-gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies.
摘要翻译： 用于管道电子处理器设备的设计结构可以体现在用于设计，制造或测试处理器集成电路的机器可读介质中。 该设计结构可以体现管道电子电路，该管道电子电路能够通过模拟来识别流水线阶段之间的时钟选通机会，从而在管线的阶段中实现功率节省。 在一个实施例中，仿真结果帮助设计者设计流水线电子电路设计结构，以通过在模拟识别的时钟选通机会位置处在管线的阶段之间并入时钟选通电路来实现功率节省。
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9.发明申请Method and Apparatus for Detecting Clock Gating Opportunities in a Pipelined Electronic Circuit Design 有权用于检测流水线电子电路设计中的时钟门控机会的方法和装置公开(公告)号：US20090055668A1
公开(公告)日：2009-02-26
申请号：US11842491
申请日：2007-08-21
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3237 , G06F9/3867 , Y02D10/128
摘要： A pipeline electronic circuit and design methodology enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit to achieve power conservation by incorporating clock-gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies.
摘要翻译： 管道电子电路和设计方法通过模拟来识别流水线各阶段之间的时钟门控机会，从而在管线的阶段实现功率节省。 在一个实施例中，模拟结果帮助设计者设计流水线电子电路，以通过在模拟识别的时钟选通机会位置处在流水线的各个阶段之间并入时钟选通电路来实现功率守恒。
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