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1.发明授权Computer with multiple processors having varying priorities for access to a multi-element memory 失效具有多个优先权的计算机，用于访问多元素存储器
公开(公告)号：US5133059A
公开(公告)日：1992-07-21
申请号：US639413
申请日：1991-01-10
CPC分类号： G06F12/084 , G06F13/18
摘要： A parallel processing computer is disclosed in which a plurality of memory elements (e.g., caches) are accessable by a plurality of processors, and in which a fixed access priority for the processors is varied periodically to reduce differences in processing times between the processors in applications where memory access conflicts occur. The variation in priority is done infrequently enough so as not to disturb the ability of the system to avoid memory access conflicts by falling into a "lockstep" condition, in which the fixed priority combined with a selected interleaving of the memory elements produces a memory access pattern that, for certain memory strides, produces no memory access conflicts.
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2.发明授权Digital computer with cache capable of concurrently handling multiple accesses from parallel processors 失效具有能够并行处理来自并行处理器的多个访问的缓存的数字计算机
公开(公告)号：US4794521A
公开(公告)日：1988-12-27
申请号：US757859
申请日：1985-07-22
CPC分类号： G06F12/084 , G06F12/0859
摘要： A cache memory capable of concurrently accepting and working on completion of more than one cache access from a plurality of processors connected in parallel. Current accesses to the cache are handled by current-access-completion circuitry which determines whether the current access is capable of immediate completion and either completes the access immediately if so capable or transfers the access to pending-access-completion circuitry if not so capable. The latter circuitry works on completion of pending accesses; it determines and stores for each pending access status information prescribing the steps required to complete the access and redetermines that status information as conditions change. In working on completion of current and pending accesses, the addresses of the accesses are compared to those of memory accesses in progress on the system.
摘要翻译： 一种高速缓冲存储器，其能够并行地接受并且从并行连接的多个处理器完成多于一个的高速缓存访问。 当前访问完成电路由当前访问完成电路来处理对高速缓存的当前访问，该电路确定当前访问是否能够立即完成，并且如果能够执行，则立即完成访问，或者如果不能够将该访问传送到等待访问完成电路。 后者的电路工作在完成未决访问; 它确定并存储规定完成访问所需步骤的每个未决访问状态信息，并根据条件改变重新确定该状态信息。 在完成当前和未完成的访问时，将访问地址与正在进行的存储器访问的地址进行比较。
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公开(公告)号：US4783736A
公开(公告)日：1988-11-08
申请号：US757853
申请日：1985-07-22
CPC分类号： G06F9/4426 , G06F12/0851 , G06F8/45
摘要： A digital computer including a plurality of memory elements, the memory elements being interleaved (i.e., each is assigned memory addresses on the basis of a low order portion of the memory address), a plurality of processors connected in parallel, the processors each having means for initiating an access of data from any of the memory elements simultaneously with accesses of other processors, the memory elements each being capable of accepting an access from just one of the processors during a given cycle, and the memory elements being interleaved so that the memory access patterns generated at a stride of one and a stride of two each meet the conditions that (1) the pattern will tolerate being offset with respect to an identical pattern by a desired offset and any multiple of the offset (wherein tolerating means that no memory access conflicts arise, i.e., more than one processor simultaneously attempting to access the same memory element) and (2) the pattern includes sufficient conflicts at offsets other than the desired offset to force the processors to assume a relationship wherein the desired offset is achieved, so that the processor is able to access a different memory element simultaneously without creating access conflicts.
摘要翻译： 一种包括多个存储元件的数字计算机，存储器元件被交错（即，基于存储器地址的低阶部分分配存储器地址），并行连接的多个处理器，每个处理器具有装置 用于启动来自任何存储器元件的数据与其他处理器的访问同时访问，每个存储器元件能够在给定周期期间仅接收来自处理器中的一个的访问，并且存储器元件被交织，使得存储器 在步幅1和步幅2中产生的访问模式都满足以下条件：（1）模式将容忍相对于相同模式偏移期望的偏移量和偏移的任何倍数（其中容忍意味着没有记忆 出现访问冲突，即，多个处理器同时尝试访问相同的存储器元件）和（2）该模式包括足够的conf 以除了期望的偏移之外的偏移量强制处理器呈现其中实现期望的偏移的关系，使得处理器能够同时访问不同的存储元件而不产生访问冲突。
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公开(公告)号：US20140036695A1
公开(公告)日：2014-02-06
申请号：US13562901
申请日：2012-07-31
申请人： Michael L. Ziegler
发明人： Michael L. Ziegler
IPC分类号： H04L12/26
CPC分类号： H04L49/901
摘要： Techniques are provided for performing a delay. A request for a delay may be received. A plurality of delay queues may be provided, with each delay queue spanning a range of delay remaining. The request may be assigned to a delay queue based on the delay remaining. The request may be moved to a different delay queue as the delay remaining decreases.
摘要翻译： 提供技术来执行延迟。 可能会收到延迟请求。 可以提供多个延迟队列，其中每个延迟队列跨越延迟范围。 可以根据剩余的延迟将请求分配给延迟队列。 随着延迟的下降，该请求可以被移动到不同的延迟队列。
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公开(公告)号：US20130223443A1
公开(公告)日：2013-08-29
申请号：US13407125
申请日：2012-02-28
申请人： Michael L. Ziegler
发明人： Michael L. Ziegler
IPC分类号： H04L12/56
CPC分类号： H04L12/56
摘要： Techniques described herein provide for sending packets to nodes based on distribution trees with stages. A packet may be received at a node. The stage of the node may be determined. A distribution tree may be selected. Based on the stage and the selected distribution tree, subsequent stage nodes may be determined. The packet may be sent to the subsequent stage nodes.
摘要翻译： 本文描述的技术提供了基于具有阶段的分布树向节点发送分组。 可以在节点处接收分组。 可以确定节点的阶段。 可以选择分配树。 根据阶段和选择的分布树，可以确定后续阶段节点。 该分组可以被发送到后续的节点。
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公开(公告)号：US20130117605A1
公开(公告)日：2013-05-09
申请号：US13288782
申请日：2011-11-03
申请人： Michael L. Ziegler , Paymon Ghamami
发明人： Michael L. Ziegler , Paymon Ghamami
IPC分类号： G06F11/07
摘要： Techniques for taking corrective action based on probabilities are provided. Request messages may include a size of a data packet and a stated issue interval. A probability of taking corrective action based on the size of the data packet, the stated issue interval, and a target issue interval may be retrieved. Corrective action may be taken with the retrieved probability.
摘要翻译： 提供了基于概率采取纠正措施的技术。 请求消息可以包括数据分组的大小和所述发布间隔。 可以检索基于数据分组的大小，所述问题间隔和目标问题间隔采取校正动作的概率。 纠正措施可以采用检索的概率。
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公开(公告)号：US20130111050A1
公开(公告)日：2013-05-02
申请号：US13286878
申请日：2011-11-01
申请人： Michael L. Ziegler
发明人： Michael L. Ziegler
IPC分类号： G06F15/16
CPC分类号： H04L12/4633 , H04L49/505
摘要： Techniques for delays based on packet sizes are provided. Request messages may identify the size of a data packet. Delays may be initiated based in part on a portion of the size of the data packet. The delays may also be based in part on target issue intervals. Request messages may be sent after the delays.
摘要翻译： 提供了基于分组大小的延迟技术。 请求消息可以标识数据分组的大小。 可以部分地基于数据分组的大小的一部分来启动延迟。 这些延误也可能部分地基于目标问题间隔。 请求消息可能会在延迟之后发送。
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公开(公告)号：US20120320909A1
公开(公告)日：2012-12-20
申请号：US13161945
申请日：2011-06-16
IPC分类号： H04L12/50
CPC分类号： H04L12/4633
摘要： Techniques described herein provide for sending request messages. The request messages may be sent in order. The request messages may be sent over a designated communications channel.
摘要翻译： 本文描述的技术提供发送请求消息。 请求消息可以按顺序发送。 请求消息可以通过指定的通信信道发送。
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9.发明申请公开(公告)号：US20080270773A1
公开(公告)日：2008-10-30
申请号：US11796810
申请日：2007-04-30
申请人： Michael L. Ziegler
发明人： Michael L. Ziegler
IPC分类号： G06F9/30
摘要： Embodiments involve an embedded processing element that fetches at least two possible next instructions (control words) in parallel in one cycle, and executes one of them during the following cycle based on the result of a conditional branch test. Embodiments reduce or avoid branch penalties (zero penalty branches).
摘要翻译： 实施例涉及在一个周期中并行获取至少两个可能的下一个指令（控制字）的嵌入式处理元件，并且基于条件分支测试的结果在随后的周期中执行它们之一。 实施例减少或避免分支惩罚（零惩罚分支）。
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公开(公告)号：US06708288B1
公开(公告)日：2004-03-16
申请号：US09702590
申请日：2000-10-31
IPC分类号： G06F1100
CPC分类号： G06F11/1407 , G06F11/1469
摘要： Compiler-based checkpointing for error recovery. In various embodiments, a compiler is adapted to identify checkpoints in program code. Sets of data objects are associated with the checkpoints, and checkpoint code is generated by the compiler for execution at the checkpoints. The checkpoint code stores state information of the associated data objects for recovery if execution of the program is interrupted.
摘要翻译： 基于编译器的检查点进行错误恢复。 在各种实施例中，编译器适于识别程序代码中的检查点。 数据对象集合与检查点相关联，检查点代码由编译器生成，以便在检查点执行。 如果程序的执行中断，则检查点代码存储用于恢复的相关联的数据对象的状态信息。
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