公开(公告)号：US06204857B1

公开(公告)日：2001-03-20

申请号：US09061383

申请日：1998-04-16

申请人： Thomas A. Piazza ,  Michael Mantor ,  Ralph Clayton Taylor ,  Val Gene Cook

发明人： Thomas A. Piazza ,  Michael Mantor ,  Ralph Clayton Taylor ,  Val Gene Cook

IPC分类号： G06T1140

CPC分类号： G06T15/04

摘要： Method and apparatus for rendering texture to an object to be displayed on a pixel screen display. This technique makes use of linear interpolation between perspectively correct texture address to calculate rates of change of individual texture addresses components to determine a selection of the correct LOD map to use and intermediate texture addresses for pixels of the object between the perspectively correct addresses. The method first determines perspectively correct texture address values associated with four corners of a predefined span or grid of pixels. Then, a linear interpolation technique is implemented to calculate a rate of change of texture address components in the screen x and y directions for pixels between the perspectively bound span corners. This linear interpolation technique is performed in both screen directions to thereby create a potentially unique level of detail value for each pixel, which is then used as an index to select the correct pre-filtered LOD texture map. When mapping an individually determined LOD value per pixel, the effect of producing undesirable artifacts that may appear if a single LOD for an entire span or polygon is used, is obviated.

摘要翻译： 用于将纹理渲染到要在像素屏幕显示上显示的对象的方法和装置。 该技术利用透视正确的纹理地址之间的线性插值来计算各个纹理地址分量的变化率，以确定正确的LOD映射的使用选择，以及在透视正确的地址之间对象的像素的中间纹理地址。 该方法首先确定与预定义跨度或像素网格的四个角相关联的透视正确的纹理地址值。 然后，实现线性插值技术，以计算在透视边界角之间的像素的屏幕x和y方向上的纹理地址分量的变化率。 这种线性插值技术在两个屏幕方向上执行，从而为每个像素创建潜在唯一的细节值级，然后将其用作选择正确的预滤波LOD纹理图的索引。 当映射每个像素的单独确定的LOD值时，如果使用整个跨度或多边形的单个LOD，则可能出现产生不期望的伪影的效果。

公开(公告)号：US06639598B2

公开(公告)日：2003-10-28

申请号：US09735037

申请日：2000-12-12

申请人： Thomas A. Piazza ,  Michael Mantor ,  Ralph Clayton Taylor ,  Val Gene Cook

发明人： Thomas A. Piazza ,  Michael Mantor ,  Ralph Clayton Taylor ,  Val Gene Cook

IPC分类号： G06T1700

CPC分类号： G06T15/04

摘要： Method and apparatus for rendering texture to an object to be displayed on a pixel screen display. This technique makes use of linear interpolation between perspectively correct texture address to calculate rates of change of individual texture addresses components to determine a selection of the correct LOD map to use and intermediate texture addresses for pixels of the object between the perspectively correct addresses. The method first determines perspectively correct texture address values associated with four corners of a predefined span or grid of pixels. Then, a linear interpolation technique is implemented to calculate a rate of change of texture address components in the screen x and y directions for pixels between the perspectively bound span corners. This linear interpolation technique is performed in both screen directions to thereby create a potentially unique level of detail value for each pixel, which is then used as an index to select the correct pre-filtered LOD texture map. When mapping an individually determined LOD value per pixel, the effect of producing undesirable artifacts that may appear if a single LOD for an entire span or polygon is used, is obviated.

摘要翻译： 用于将纹理渲染到要在像素屏幕显示上显示的对象的方法和装置。 该技术利用透视正确的纹理地址之间的线性内插来计算单个纹理地址分量的变化率，以确定正确的LOD图的使用选择，以及在透视正确的地址之间对象的像素的中间纹理地址。 该方法首先确定与预定义跨度或像素网格的四个角相关联的透视正确的纹理地址值。 然后，实现线性插值技术，以计算在透视边界角之间的像素的屏幕x和y方向上的纹理地址分量的变化率。 这种线性插值技术在两个屏幕方向上执行，从而为每个像素创建潜在唯一的细节值级，然后将其用作选择正确的预滤波LOD纹理图的索引。 当映射每个像素的单独确定的LOD值时，如果使用整个跨度或多边形的单个LOD，则可能出现产生不期望的伪影的效果。

公开(公告)号：US06191793B1

公开(公告)日：2001-02-20

申请号：US09053591

申请日：1998-04-01

申请人： Thomas A. Piazza ,  Michael Mantor ,  Ralph Clayton Taylor ,  Steven Manno

发明人： Thomas A. Piazza ,  Michael Mantor ,  Ralph Clayton Taylor ,  Steven Manno

IPC分类号： G06T1140

CPC分类号： G06T15/04

摘要： A computationally efficient method for minimizing the visible effects of texture LOD transitions across a polygon. The minimization is accomplished by adding a dithering offset value to the LOD value computed for each pixel covered by a graphics primitive to produce a dithered pixel LOD value. The dithering offsets mat be generated from a table look-up based on the location of the pixel within a span of pixels. The dithered pixel LOD value is used to as an index in the selection of a single LOD texture map from which a textured pixel value is retrieved. The range of dithering offset values can be adjusted by modulating the values in the table look-up.

摘要翻译： 一种用于最小化跨多边形的纹理LOD转换的可见效果的计算有效的方法。 通过向由图形基元覆盖的每个像素计算的LOD值添加抖动偏移值以产生抖动像素LOD值来实现最小化。 基于像素跨度内的像素的位置，从表查找生成抖动偏移量。 抖动像素LOD值用于选择单个LOD纹理图的索引，从其中检索纹理像素值。 可以通过调整表查找中的值来调整抖动偏移值的范围。

公开(公告)号：US6072505A

公开(公告)日：2000-06-06

申请号：US53589

申请日：1998-04-01

申请人： Thomas A. Piazza ,  R. Scott Hartog ,  Michael Mantor ,  Jeffrey D. Potter ,  Ralph Clayton Taylor ,  Michael A. Mang

发明人： Thomas A. Piazza ,  R. Scott Hartog ,  Michael Mantor ,  Jeffrey D. Potter ,  Ralph Clayton Taylor ,  Michael A. Mang

IPC分类号： G06T3/40 ,  G06T1/00 ,  G06F15/00

CPC分类号： G06T3/403

摘要： A rasterizer comprised of a bounding box calculator, a plane converter, a windower, and incrementers. For each polygon to be processed, a bounding box calculation is performed which determines the display screen area, in spans, that totally encloses the polygon and passes the data to the plane converter. The plane converter also receives as input attribute values for each vertex of the polygon. The plane converter computes planar coefficients for each attribute of the polygon, for each of the edges of the polygon. The plane converter unit computes the start pixel center location at a start span and a starting coefficient value at that pixel center. The computed coefficients also include the rate of change or gradient, for each polygon attribute in the x and y directions, respectively. The plane converter also computes line coefficients for each of the edges of the polygon. Line equation values are passed through to the windower where further calculations allow the windower to determine which spans are either covered or intersected by the polygon. The incrementers receive the span coverage data from the windower in addition to receiving planar coefficient values from the plane converter. The incrementers utilize the data from both the windower and plane converter to walk or traverse the polygon in those intersected spans, pixel by pixel. As the incrementer visits each pixel, vertex attribute values are interpolated to each pixel.

摘要翻译： 由边界计算器，平面转换器，加窗器和加法器构成的光栅化器。 对于要处理的每个多边形，执行边界框计算，其确定完全包围多边形并将数据传递到平面转换器的跨度的显示屏幕区域。 平面转换器还接收多边形的每个顶点的输入属性值。 平面转换器为多边形的每个边缘计算多边形的每个属性的平面系数。 平面转换器单元计算开始跨度处的开始像素中心位置和该像素中心处的起始系数值。 所计算的系数也分别包括x和y方向上每个多边形属性的变化率或梯度。 平面转换器还为多边形的每个边缘计算线系数。 线路方程值被传递到风力发电机，进一步的计算允许风轮确定哪个跨度被多边形覆盖或相交。 除了从平面转换器接收平面系数值之外，增量器还接收来自风力发电机的跨距覆盖数据。 增量器利用来自两台风力发电机和平面转换器的数据逐行扫描或横穿那些相交的跨度中的多边形。 随着增量器访问每个像素，顶点属性值被内插到每个像素。

公开(公告)号：US07050063B1

公开(公告)日：2006-05-23

申请号：US09502994

申请日：2000-02-11

申请人： Michael Mantor ,  John Austin Carey ,  Ralph Clayton Taylor ,  Thomas A. Piazza ,  Jeffrey D. Potter ,  Angel E. Socarras

发明人： Michael Mantor ,  John Austin Carey ,  Ralph Clayton Taylor ,  Thomas A. Piazza ,  Jeffrey D. Potter ,  Angel E. Socarras

IPC分类号： G09G5/00

CPC分类号： G09G5/39 ,  G06T1/60 ,  G06T15/04 ,  G09G3/003 ,  G09G2360/121

摘要： A 3D rendering texture caching scheme that minimizes external bandwidth requirements for texture and increases the rate at which textured pixels are available. The texture caching scheme efficiently pre-fetches data at the main memory access granularity and stores it in cache memory. The data in the main memory and texture cache memory is organized in a manner to achieve large reuse of texels with a minimum of cache memory to minimize cache misses. The texture main memory stores a two dimensional array of texels, each texel having an address and one of N identifiers. The texture cache memory has addresses partitioned into N banks, each bank containing texels transferred from the main memory that have the corresponding identifier. A cache controller determines which texels need to be transferred from the texture main memory to the texture cache memory and which texels are currently in the cache using a least most recently used algorithm. By labeling the texture map blocks (double quad words), a partitioning scheme is developed which allow the cache controller structure to be very modular and easily realized. The texture cache arbiter is used for scheduling and controlling the actual transfer of texels from the texture main memory into the texture cache memory and controlling the outputting of texels for each pixel to an interpolating filter from the cache memory.

摘要翻译： 3D渲染纹理缓存方案，可最大限度地减少纹理的外部带宽需求，并提高纹理像素可用的速率。 纹理缓存方案有效地预取主存储器访问粒度的数据并将其存储在高速缓冲存储器中。 主存储器和纹理高速缓冲存储器中的数据被组织成以最小的高速缓冲存储器实现大量的纹理复用的重用，以最小化高速缓存未命中。 纹理主存储器存储纹素的二维阵列，每个纹素具有地址和N个标识符之一。 纹理高速缓冲存储器具有分割成N个存储体的地址，每个存储体包含从主存储器传送的具有相应标识符的纹素。 高速缓存控制器使用最近最少使用的算法来确定哪个纹素需要从纹理主存储器传送到纹理高速缓存存储器以及哪个纹素目前在高速缓存中。 通过标记纹理贴图块（双四字），开发了一种分区方案，允许高速缓存控制器结构非常模块化，轻松实现。 纹理高速缓存仲裁器用于调度和控制纹理主体存储器到纹理高速缓存存储器中的纹素的实际传输，并且控制从高速缓冲存储器输出每个像素的纹理像素到内插滤波器。

公开(公告)号：US06433790B1

公开(公告)日：2002-08-13

申请号：US09234133

申请日：1999-01-19

申请人： Ralph Clayton Taylor ,  Daniel B. Clifton ,  David Gotwalt ,  Michael A. Mang ,  Thomas A. Piazza ,  Jeffrey D. Potter

发明人： Ralph Clayton Taylor ,  Daniel B. Clifton ,  David Gotwalt ,  Michael A. Mang ,  Thomas A. Piazza ,  Jeffrey D. Potter

IPC分类号： G09G536

CPC分类号： G06T11/203 ,  G06T11/40 ,  G09G5/026 ,  G09G5/20

摘要： A method and system for rendering a feature, such as a line, for display on an array of pixels. With this method, the line is identified on the pixel array, the line is expanded into a polygon, and color values are determined for the pixels within the polygon. Also, an antialiasing region is identified in the polygon, and blend values are computed for the pixels in this antialiasing region. Then, the color values determined for the pixels in the antialiasing region are modified as a function of these computed blend values. The pixels in the antialiasing region may then be shown at their modified color values, while the pixels that are in the polygon but not in the antialising region may be shown at their original determined color value. Preferably, the blend values for the pixels in the antialiasing region are calculated as a function of the locations of the pixels in that region. For example, the blend value for each of these pixels may be calculated as a function of four values, each one representing the Manhattan distance from the pixel to a respective one of the edges of the polygon. Also, preferably the antialiasing region has a uniform width, and this region extends inward from side edges and outward from end edges of the formed polygon.

摘要翻译： 用于渲染诸如线的特征的方法和系统，用于在像素阵列上显示。 使用该方法，在像素阵列上识别线，将线扩展为多边形，并且确定多边形内的像素的颜色值。 此外，在多边形中识别抗混叠区域，并且为该抗混叠区域中的像素计算混合值。 然后，针对抗锯齿区域中的像素确定的颜色值被修改为这些计算的混合值的函数。 然后可以以其修改的颜色值示出抗锯齿区域中的像素，而可以以其原始确定的颜色值示出处于多边形但不在反偏移区域中的像素。 优选地，根据该区域中的像素的位置来计算抗锯齿区域中的像素的混合值。 例如，可以将这些像素中的每一个的混合值计算为四个值的函数，每个值表示从像素到多边形的相应边缘的曼哈顿距离。 此外，优选地，抗锯齿区域具有均匀的宽度，并且该区域从侧边缘向内延伸并且从形成的多边形的端边缘向外延伸。

公开(公告)号：US20140359220A1

公开(公告)日：2014-12-04

申请号：US14122256

申请日：2013-05-31

申请人： Altug Koker ,  Thomas A. Piazza ,  Murali Sundaresan

发明人： Altug Koker ,  Thomas A. Piazza ,  Murali Sundaresan

IPC分类号： G06F12/08

CPC分类号： G06F12/0804 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0822 ,  G06F12/0831 ,  G06F12/0846 ,  G06F12/0853 ,  G06F12/0875 ,  G06F12/128 ,  G06F2212/621

摘要： In accordance with some embodiments, a scatter/gather memory approach may be enabled that is exposed or backed by system memory and uses conventional tags and addresses. Thus, such a technique may be more amenable to conventional software developers and their conventional techniques.

摘要翻译： 根据一些实施例，可以启用由系统存储器公开或支持并使用常规标签和地址的分散/收集存储器方法。 因此，这种技术可能更适合于常规软件开发人员及其常规技术。

公开(公告)号：US08544019B2

公开(公告)日：2013-09-24

申请号：US13116245

申请日：2011-05-26

申请人： Hong Jiang ,  Thomas A. Piazza ,  Brian D. Rauchfuss ,  Sreedevi Chalasani ,  Steven J. Spangler

发明人： Hong Jiang ,  Thomas A. Piazza ,  Brian D. Rauchfuss ,  Sreedevi Chalasani ,  Steven J. Spangler

IPC分类号： G06F9/46 ,  G06F15/00

CPC分类号： G06F9/546

摘要： In some embodiments, a method includes receiving a request to generate a thread and supplying a request to a queue in response at least to the received request. The method may further include fetching a plurality of instructions in response at least in part to the request supplied to the queue and executing at least one of the plurality of instructions. In some embodiments, an apparatus includes a storage medium having stored therein instructions that when executed by a machine result in the method. In some embodiments, an apparatus includes circuitry to receive a request to generate a thread and to queue a request to generate a thread in response at least to the received request. In some embodiments, a system includes circuitry to receive a request to generate a thread and to queue a request to generate a thread in response at least to the received request, and a memory unit to store at least one instruction for the thread.

摘要翻译： 在一些实施例中，一种方法包括接收生成线程的请求并至少响应于所接收的请求向队列提供请求。 该方法还可以包括至少部分地响应于提供给队列的请求并且执行多个指令中的至少一个指令来获取多个指令。 在一些实施例中，装置包括存储介质，其中存储有当机器执行时产生该方法的指令。 在一些实施例中，一种装置包括用于接收生成线程的请求并至少对接收到的请求作出响应来排队请求生成线程的电路。 在一些实施例中，系统包括电路，用于接收生成线程的请求，并至少响应于所接收到的请求来对请求进行排队以生成线程;以及存储器单元，用于存储线程的至少一条指令。

公开(公告)号：US20120272032A1

公开(公告)日：2012-10-25

申请号：US13534259

申请日：2012-06-27

申请人： Thomas A. Piazza

发明人： Thomas A. Piazza

IPC分类号： G06F12/02

CPC分类号： G06F9/5016 ,  G06F12/023

摘要： A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using the ranges of addresses. Different ranges of addresses in the memory may be redistributed among a second set of functions in a second pipeline without waiting for the first set of functions to be flushed of data.

摘要翻译： 一种方法可以包括在第一流水线中的第一组函数中分配存储器中的地址范围。 第一管道中的第一组功能可以使用地址范围对数据进行操作。 可以在第二流水线中的第二组功能中重新分配存储器中的不同范围的地址，而不等待第一组功能被刷新数据。

公开(公告)号：US20090248983A1

公开(公告)日：2009-10-01

申请号：US12057601

申请日：2008-03-28

申请人： Zeev Offen ,  Ariel Berkovits ,  Thomas A. Piazza ,  Robert L. Farrell ,  Altug Koker ,  Opher Kahn

发明人： Zeev Offen ,  Ariel Berkovits ,  Thomas A. Piazza ,  Robert L. Farrell ,  Altug Koker ,  Opher Kahn

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F12/0811 ,  G06F12/0822 ,  G06F12/0828 ,  G06F12/0835 ,  G06F13/1668 ,  G06F13/28 ,  G06F13/4282 ,  G06F2212/283 ,  G06F2212/60 ,  G06F2212/621 ,  G06F2213/0026 ,  G06T1/60 ,  G11C7/1072

摘要： A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

摘要翻译： 一种能够在不同高速缓存一致性域内的代理之间进行信息共享的技术。 在一个实施例中，图形设备可以使用一个或多个处理核心使用的一个或多个高速缓存来存储或读取信息，这些信息可以由一个或多个处理核心以不影响与编程相关的编程和一致性规则的方式来访问 图形设备。