公开(公告)号：US20060044049A1

公开(公告)日：2006-03-02

申请号：US10711205

申请日：2004-09-01

申请人： Michael Ouellette ,  Larry Wissel

发明人： Michael Ouellette ,  Larry Wissel

IPC分类号： H01H37/76

CPC分类号： G11C29/027 ,  G11C17/14 ,  G11C17/16 ,  G11C17/18 ,  G11C29/02 ,  G11C29/50 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electronic fuse structure is disclosed for integrated circuits that is programmable with low voltage and incorporates a differential sensing scheme. The programming step is performed at about 1.5 times Vdd while the sense operation is performed at Vdd, which limits the resistance variation through the electronic fuse caused by the sense operation. During the sense operation a gating transistor emulates the voltage drop across a fuse select transistor for the case of an intact fuse. A circuit and method for characterizing the resistance of the electronic fuse is also disclosed.

摘要翻译： 公开了一种用于低电压编程的集成电路的电子熔丝结构，并结合了差分感测方案。 在Vdd执行感测操作时，以大约1.5倍的Vdd执行编程步骤，这限制了由感测操作引起的电子熔断器的电阻变化。 在感测操作期间，门控晶体管模拟保险丝选择晶体管上的电压降，用于完整的熔丝的情况。 还公开了用于表征电子熔断器的电阻的电路和方法。

公开(公告)号：US20060059393A1

公开(公告)日：2006-03-16

申请号：US11270411

申请日：2005-11-08

申请人： Jeffrey Oppold ,  Michael Ouellette ,  Larry Wissel

发明人： Jeffrey Oppold ,  Michael Ouellette ,  Larry Wissel

IPC分类号： G11C29/00 ,  H03M13/00

CPC分类号： G11C5/005 ,  G11C11/4125 ,  G11C29/787

摘要： A redundancy register architecture associated with a RAM provides for soft-error tolerance. An enable register provides soft error rate protection to the registers that contain replacement information for redundant rows and columns. The gate register determines whether a row or column replacement register contains a specific address, and parity protection to the replacement register is activated as necessitated. The register architecture is changed to make the register state a “don't care” state for the majority of the registers. A small number of registers that are critical to the redundancy system are identified and made more robust to upsets. Word-line and column-line substitution is implemented. A ripple parity scheme is implemented when parity checks are activated.

摘要翻译： 与RAM相关联的冗余寄存器架构提供了软错误容限。 启用寄存器为包含冗余行和列的替换信息的寄存器提供软错误率保护。 门寄存器确定行或列替换寄存器是否包含特定地址，并且根据需要激活替换寄存器的奇偶校验保护。 更改寄存器架构，使寄存器状态成为大多数寄存器的“无关”状态。 识别对冗余系统至关重要的少量寄存器，并使其变得更加鲁棒。 实现字线和列行替代。 当奇偶校验被激活时，实现纹波奇偶校验方案。

公开(公告)号：US20200029542A1

公开(公告)日：2020-01-30

申请号：US15998281

申请日：2018-07-30

申请人： Michael Ouellette

发明人： Michael Ouellette

IPC分类号： A01K97/08 ,  A01K87/02 ,  A01K87/04

摘要： This invention provides an outrigger assembly for fishing that can be quickly deployed from a portable bag about 1 meter long into a fully rigged outrigger in a selected length of 4 meters, 5 meters or 6 meters. Variable length is obtained by adding sections of telescoping pole. Quick deployment is obtained by using detachable line guides that are radially (or side) threadable in conjunction with a separate preassembled outrigger line loop for each deployed length. Different length outrigger line loop assemblies are color coded for quick identification. Stowed length and volume of the collapsed telescoping pole is minimized by the use of outrigger line guides that are removable from the outrigger pole. Threading and unthreading of an outrigger line loop without opening the loop is enabled by the radially threadable line guides. The invention also provides an outrigger holder having two sockets, one for the outrigger and one for a fishing pole.

公开(公告)号：US20080037341A1

公开(公告)日：2008-02-14

申请号：US11875011

申请日：2007-10-19

申请人： Michael Ouellette ,  Jeremy Rowland

发明人： Michael Ouellette ,  Jeremy Rowland

IPC分类号： G11C29/00

CPC分类号： G11C29/4401 ,  G11C29/14 ,  G11C29/24 ,  G11C29/44

摘要： Methods and apparatuses for enabling a redundant memory element (20) during testing of a memory array (14). The memory array (14) includes general memory elements (18) and redundant memory elements (20). The general memory elements (18) are tested and any defective general memory elements (18) are replaced with redundant memory elements (20). The redundant memory elements (20) are tested only when they are enabled.

摘要翻译： 用于在存储器阵列（14）的测试期间启用冗余存储元件（20）的方法和装置。 存储器阵列（14）包括通用存储元件（18）和冗余存储元件（20）。 一般存储器元件（18）被测试，并且任何有缺陷的通用存储器元件（18）被替换为冗余存储元件（20）。 冗余存储器元件（20）仅在使能时被测试。

公开(公告)号：US20070258296A1

公开(公告)日：2007-11-08

申请号：US11418052

申请日：2006-05-04

申请人： Arthur Bright ,  Paul Crumley ,  Marc Dombrowa ,  Steven Douskey ,  Rudolf Haring ,  Steven Oakland ,  Michael Ouellette ,  Scott Strissel

发明人： Arthur Bright ,  Paul Crumley ,  Marc Dombrowa ,  Steven Douskey ,  Rudolf Haring ,  Steven Oakland ,  Michael Ouellette ,  Scott Strissel

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/4401 ,  G11C29/802

摘要： Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

摘要翻译： 公开了一种修复包括多个存储器阵列的类型的集成电路的方法，以及用于控制用于控制阵列的冗余逻辑的控制数据的保险丝盒。 该方法包括以下步骤：向集成电路提供控制数据选择器，用于将控制数据从保险丝盒传送到存储器阵列; 提供备用控制数据源，集成电路外部; 并将替代控制数据源连接到控制数据选择器。 该方法还包括在给定时间，通过控制数据选择器将备用控制数据从其源传递到存储器阵列以控制存储器阵列的冗余逻辑的步骤。

公开(公告)号：US20070230260A1

公开(公告)日：2007-10-04

申请号：US11278238

申请日：2006-03-31

申请人： Kevin Gorman ,  Emory Keller ,  Michael Ouellette

发明人： Kevin Gorman ,  Emory Keller ,  Michael Ouellette

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/16 ,  G11C2029/5002

摘要： A Built-In-Self-Test (BIST) state machine providing BIST testing operations associated with a thermal sensor device(s) located in proximity to the circuit(s) to which BIST testing operations are applied. The thermal sensor device compares the current temperature value sensed to a predetermined temperature threshold and determines whether the predetermined threshold is exceeded. A BIST control element suspends the BIST testing operation in response to meeting or exceeding said predetermined temperature threshold, and initiates resumption of BIST testing operations when the current temperature value normalizes or is reduced. A BIST testing methodology implements steps for mitigating the exceeded temperature threshold condition in response to determining that the predetermined temperature threshold is met or exceeded. These steps include one of: ignoring the BIST results of the suspect circuit(s), or by causing the BIST state machine to enter a wait state and adjusting operating parameters of the suspect circuits while in the wait state.

摘要翻译： 内置自测试（BIST）状态机，提供与位于BIST测试操作所在电路附近的热传感器设备相关的BIST测试操作。 热传感器装置将感测到的当前温度值与预定温度阈值进行比较，并确定是否超过预定阈值。 BIST控制元件响应于满足或超过所述预定温度阈值而暂停BIST测试操作，并且当当前温度值归一化或降低时，启动BIST测试操作的恢复。 响应于确定满足或超过预定温度阈值，BIST测试方法实现了减轻超过温度阈值条件的步骤。 这些步骤包括：忽略可疑电路的BIST结果，或通过使BIST状态机进入等待状态，并在等待状态下调整可疑电路的工作参数。

公开(公告)号：US20050270866A1

公开(公告)日：2005-12-08

申请号：US11160268

申请日：2005-06-16

申请人： Michael Ouellette ,  Jeremy Rowland

发明人： Michael Ouellette ,  Jeremy Rowland

IPC分类号： G11C29/00 ,  G11C29/14 ,  G11C29/24 ,  G11C29/44

CPC分类号： G11C29/4401 ,  G11C29/14 ,  G11C29/24 ,  G11C29/44

摘要： Methods and apparatuses for enabling a redundant memory element (20) during testing of a memory array (14).

摘要翻译： 用于在存储器阵列（14）的测试期间启用冗余存储元件（20）的方法和装置。

公开(公告)号：US20050013187A1

公开(公告)日：2005-01-20

申请号：US10604414

申请日：2003-07-18

申请人： Darren Anand ,  John Barth ,  Steven Oakland ,  Michael Ouellette

发明人： Darren Anand ,  John Barth ,  Steven Oakland ,  Michael Ouellette

IPC分类号： G11C17/00 ,  G11C17/16 ,  G11C17/18

CPC分类号： G11C17/16 ,  G11C17/18

摘要： A method and electrical fuse circuit design for reducing the testing time for a semiconductor device manufactured with redundant eFuse circuitry. A two-to-one multiplexer (MUX) is provided at each eFuse circuit in addition to the fuse latch and pattern latch and other logic components the eFuse circuit. Information on which fuse is to be blown is stored in the fuse's pattern latch. The output generated by the pattern latch is ANDed with a program input to provide a select signal for the MUX. Based on the select signal, the MUX allows the shifted “1” to either go to the next latch in the shift chain or bypass the next latch or latches in the shift chain depending on whether the next fuse is to be blown. Accordingly, rather than serially shifting through each fuse latch within the device, the invention enables only those fuse latches associated with fuses that are to be blown to hold up the propagation of the shifted “1” to the next eFuse circuits.

摘要翻译： 一种用于减少使用冗余eFuse电路制造的半导体器件的测试时间的方法和电熔丝电路设计。 除了保险丝锁存器和图案锁存器以及eFuse电路的其他逻辑元件之外，在每个eFuse电路上还提供两对一多路复用器（MUX）。 保险丝图案锁存器中存储有要熔断保险丝的信息。 由模式锁存器产生的输出与程序输入进行“与”运算以提供MUX的选择信号。 基于选择信号，MUX允许移位的“1”转到下一个锁存器，或者旁路下一个锁存器或锁存在换档链中，这取决于下一个保险丝是否被熔断。 因此，本发明不仅可以串联地转换器件内的每个熔丝锁存器，而且仅使与熔断器相关联的熔丝锁存器能够保持传输“1”到下一个eFuse电路的传输。

公开(公告)号：US20080022149A1

公开(公告)日：2008-01-24

申请号：US11829187

申请日：2007-07-27

申请人： Michael Ouellette ,  Jeremy Rowland

发明人： Michael Ouellette ,  Jeremy Rowland

IPC分类号： G06F11/08

CPC分类号： G11C29/14 ,  G11C29/24 ,  G11C29/44 ,  G11C29/4401

摘要： A design structure embodied in a machine readable medium for designing, manufacturing, testing and/or enabling a redundant memory element (20) during testing of a memory array (14), and a method of repairing a memory array.

摘要翻译： 体现在用于在存储器阵列（14）的测试期间设计，制造，测试和/或启用冗余存储器元件（20）的机器可读介质中的设计结构以及修复存储器阵列的方法。

公开(公告)号：US20060239088A1

公开(公告)日：2006-10-26

申请号：US10908033

申请日：2005-04-26

申请人： Darren Anand ,  Michael Ouellette ,  Michael Ziegerhofer

发明人： Darren Anand ,  Michael Ouellette ,  Michael Ziegerhofer

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C17/165 ,  G11C29/027 ,  G11C29/4401 ,  G11C29/72

摘要： Integrated circuit memory is tested to discover defective memory elements. To replace the defective memory elements, spare memory elements are selected and a string is generated to indicate which ones of the spares replace which ones of the defective memory elements. The number of bits of the string depend upon how many of the memory elements are defective. Although a certain number of the memory elements are defective, which determines the number of the string bits, nevertheless, a number of fuses to program on the integrated circuit is determined responsive to how many fuses are available for programming relative to the number of the binary string bits. That is, if more fuses are available than a certain threshold number relative to the number of string bits (as is preferred), then more than the threshold number are programmed. If not, then only that certain threshold number of fuses are programmed.

摘要翻译： 测试集成电路存储器以发现有缺陷的存储器元件。 为了更换有缺陷的存储器元件，选择备用存储器元件，并且生成字符串以指示哪些备用件替换有缺陷存储器元件中的哪一个。 字符串的位数取决于多少存储器元件有缺陷。 尽管一定数量的存储器元件是有缺陷的，这确定了串比特的数目，然而，确定集成电路上编程的多个保险丝的响应是相对于二进制数的编号有多少个熔丝可用于编程 字符串位。 也就是说，如果比相对于字符串位数（优选的）更多的熔丝可用于某个阈值数，则多于阈值编号。 如果没有，那么只有该阈值数量的保险丝被编程。