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1.发明申请PCB INCLUDING MULTIPLE CHIPS SHARING AN OFF-CHIP MEMORY, A METHOD OF ACCESSING OFF-CHIP MEMORY AND A MCM UTILIZING FEWER OFF-CHIP MEMORIES THAN CHIPS 审中-公开PCB包括多个CHIPS共享一个片外存储器，一种使用片外存储器的方法和一个使用更快的片外存储器的MCM公开(公告)号：US20100017569A1
公开(公告)日：2010-01-21
申请号：US12174566
申请日：2008-07-16
IPC分类号： G06F12/00
CPC分类号： G06F12/0284
摘要： A PCB having fewer off-chip memories than chips, a MCM, and a method of accessing an off-chip shared memory space. In one embodiment, the method includes: (1) generating a memory request at a first chip of the printed circuit board, (2) transforming the memory request to a shared memory request and (3) directing the shared memory request to an off-chip shared memory space indirectly coupled to the first chip via a second chip of the printed circuit board.
摘要翻译： 具有比芯片更少的片外存储器的PCB，MCM以及访问片外共享存储器空间的方法。 在一个实施例中，该方法包括：（1）在印刷电路板的第一芯片处产生存储器请求，（2）将存储器请求转换为共享存储器请求，以及（3）将共享存储器请求引导到关闭状态， 通过印刷电路板的第二芯片间接地耦合到第一芯片的芯片共享存储器空间。
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2.发明申请Integrated Circuit Performance Enhancement Using On-Chip Adaptive Voltage Scaling 失效使用片上自适应电压调节的集成电路性能增强公开(公告)号：US20100115475A1
公开(公告)日：2010-05-06
申请号：US12261738
申请日：2008-10-30
申请人： Michael S. Buonpane , James D. Chlipala , Richard P. Martin , Richard Muscavage , Scott A. Segan
发明人： Michael S. Buonpane , James D. Chlipala , Richard P. Martin , Richard Muscavage , Scott A. Segan
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , G06F2217/78
摘要： Techniques for enhancing the performance of an IC are provided. A method of enhancing IC performance includes the steps of: associating at least one performance result of at least one performance monitor, formed on the IC, with deterministic combinations of IC performance and a processing parameter, a supply voltage, and/or a temperature of the IC; determining an IC processing characterization of the IC as a function of the performance result for at least one prescribed supply voltage and temperature of the IC, the IC processing characterization being indicative of a type of processing received by the IC during fabrication of the IC; and controlling a voltage supplied to at least a portion of the IC, the voltage being controlled as a function of the IC processing characterization and/or the temperature of the IC so as to satisfy at least one prescribed performance parameter of the IC.
摘要翻译： 提供了用于提高IC性能的技术。 一种提高IC性能的方法包括以下步骤：将形成在IC上的至少一个性能监视器的至少一个性能结果与IC性能与处理参数，电源电压和/或 IC; 根据IC的至少一个规定电源电压和温度的性能结果确定IC的IC处理特征，IC处理特性表示IC在制造IC期间接收的处理类型; 以及控制提供给所述IC的至少一部分的电压，所述电压作为所述IC处理特征和/或所述IC的温度的函数被控制，以满足所述IC的至少一个规定的性能参数。
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公开(公告)号：US09158359B2
公开(公告)日：2015-10-13
申请号：US13428862
申请日：2012-03-23
申请人： Michael S. Buonpane , James D. Chlipala , Richard P. Martin , Richard Muscavage , Scott A. Segan
发明人： Michael S. Buonpane , James D. Chlipala , Richard P. Martin , Richard Muscavage , Scott A. Segan
CPC分类号： G06F1/3209 , G06F1/325 , G06F1/3296 , Y02D10/172 , Y10T307/406
摘要： An adaptive voltage scaling system includes first and second devices. Each of the first and second devices includes at least one master serial interface port and at least one slave serial interface port. The first device is operatively coupled to a voltage regulator, and the slave serial interface port associated with the second device is operatively coupled to the master serial interface port associated with the first device. The first device controls the voltage regulator based on information obtained from the first and second devices using the master serial interface port associated with the first device and the slave serial interface port associated with the second device. The first and second devices receive voltage from the voltage regulator. A corresponding method and computer-readable medium are also disclosed.
摘要翻译： 自适应电压缩放系统包括第一和第二装置。 第一和第二设备中的每一个包括至少一个主串行接口端口和至少一个从串行接口端口。 第一设备可操作地耦合到电压调节器，并且与第二设备相关联的从串行接口端口可操作地耦合到与第一设备相关联的主串行接口端口。 第一设备使用与第一设备相关联的主串行接口端口和与第二设备相关联的从串行接口端口，基于从第一和第二设备获得的信息来控制电压调节器。 第一和第二器件从电压调节器接收电压。 还公开了相应的方法和计算机可读介质。
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公开(公告)号：US20130249290A1
公开(公告)日：2013-09-26
申请号：US13428862
申请日：2012-03-23
申请人： Michael S. Buonpane , James D. Chlipala , Richard P. Martin , Richard Muscavage , Scott A. Segan
发明人： Michael S. Buonpane , James D. Chlipala , Richard P. Martin , Richard Muscavage , Scott A. Segan
IPC分类号： H02J1/00
CPC分类号： G06F1/3209 , G06F1/325 , G06F1/3296 , Y02D10/172 , Y10T307/406
摘要： An adaptive voltage scaling system includes first and second devices. Each of the first and second devices includes at least one master serial interface port and at least one slave serial interface port. The first device is operatively coupled to a voltage regulator, and the slave serial interface port associated with the second device is operatively coupled to the master serial interface port associated with the first device. The first device controls the voltage regulator based on information obtained from the first and second devices using the master serial interface port associated with the first device and the slave serial interface port associated with the second device. The first and second devices receive voltage from the voltage regulator. A corresponding method and computer-readable medium are also disclosed.
摘要翻译： 自适应电压缩放系统包括第一和第二装置。 第一和第二设备中的每一个包括至少一个主串行接口端口和至少一个从串行接口端口。 第一设备可操作地耦合到电压调节器，并且与第二设备相关联的从串行接口端口可操作地耦合到与第一设备相关联的主串行接口端口。 第一设备使用与第一设备相关联的主串行接口端口和与第二设备相关联的从串行接口端口，基于从第一和第二设备获得的信息来控制电压调节器。 第一和第二器件从电压调节器接收电压。 还公开了相应的方法和计算机可读介质。
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5.发明授权Integrated circuit performance enhancement using on-chip adaptive voltage scaling 失效使用片上自适应电压调整的集成电路性能提升公开(公告)号：US08161431B2
公开(公告)日：2012-04-17
申请号：US12261738
申请日：2008-10-30
申请人： Michael S. Buonpane , James D. Chlipala , Richard P. Martin , Richard Muscavage , Scott A. Segan
发明人： Michael S. Buonpane , James D. Chlipala , Richard P. Martin , Richard Muscavage , Scott A. Segan
CPC分类号： G06F17/5063 , G06F2217/78
摘要： Techniques for enhancing the performance of an IC are provided. A method of enhancing IC performance includes the steps of: associating at least one performance result of at least one performance monitor, formed on the IC, with deterministic combinations of IC performance and a processing parameter, a supply voltage, and/or a temperature of the IC; determining an IC processing characterization of the IC as a function of the performance result for at least one prescribed supply voltage and temperature of the IC, the IC processing characterization being indicative of a type of processing received by the IC during fabrication of the IC; and controlling a voltage supplied to at least a portion of the IC, the voltage being controlled as a function of the IC processing characterization and/or the temperature of the IC so as to satisfy at least one prescribed performance parameter of the IC.
摘要翻译： 提供了用于提高IC性能的技术。 一种提高IC性能的方法包括以下步骤：将形成在IC上的至少一个性能监视器的至少一个性能结果与IC性能与处理参数，电源电压和/或 IC; 根据IC的至少一个规定电源电压和温度的性能结果确定IC的IC处理特征，IC处理特性表示IC在制造IC期间接收的处理类型; 以及控制提供给所述IC的至少一部分的电压，所述电压作为所述IC处理特征和/或所述IC的温度的函数被控制，以满足所述IC的至少一个规定的性能参数。
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6.发明授权Method and apparatus for deriving an integrated circuit (IC) clock with a frequency offset from an IC system clock 有权用于从IC系统时钟频率偏移导出集成电路（IC）时钟的方法和装置公开(公告)号：US07786814B2
公开(公告)日：2010-08-31
申请号：US12199881
申请日：2008-08-28
IPC分类号： H03B5/24
CPC分类号： H03K5/00006 , H03K5/135
摘要： Generally, methods and apparatus are provided for deriving an integrated circuit (IC) clock signal with a frequency that is offset from the IC system clock. An offset clock having a frequency that is offset from a system clock is generated by configuring a ring oscillator in a first mode to generate the system clock having a desired frequency; and adjusting the configuration of the ring oscillator in a second mode to generate the offset clock having the frequency that is offset from the system clock. The configuration of the ring oscillator is adjusted in the second mode by adjusting (i) a power supply value applied to the ring oscillator in the second mode relative to a power supply value applied in the first mode; or (ii) a number of delay line elements that are active in the ring oscillator loop.
摘要翻译： 通常，提供了用于导出具有偏离IC系统时钟的频率的集成电路（IC）时钟信号的方法和装置。 通过以第一模式配置环形振荡器来产生具有偏离系统时钟的频率的偏移时钟，以产生具有期望频率的系统时钟; 以及在第二模式中调整环形振荡器的配置以产生具有偏离系统时钟的频率的偏移时钟。 通过调整（i）相对于在第一模式中施加的电源值，以第二模式施加到环形振荡器的电源值，调节环形振荡器的配置在第二模式中; 或（ii）在环形振荡器回路中有效的多个延迟线元件。
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7.发明申请METHOD AND APPARATUS FOR DERIVING AN INTEGRATED CIRCUIT (IC) CLOCK WITH A FREQUENCY OFFSET FROM AN IC SYSTEM CLOCK 有权用于从集成电路系统时钟频率偏移传输集成电路（IC）时钟的方法和装置公开(公告)号：US20100052800A1
公开(公告)日：2010-03-04
申请号：US12199881
申请日：2008-08-28
IPC分类号： H03K3/03
CPC分类号： H03K5/00006 , H03K5/135
摘要： Generally, methods and apparatus are provided for deriving an integrated circuit (IC) clock signal with a frequency that is offset from the IC system clock. An offset clock having a frequency that is offset from a system clock is generated by configuring a ring oscillator in a first mode to generate the system clock having a desired frequency; and adjusting the configuration of the ring oscillator in a second mode to generate the offset clock having the frequency that is offset from the system clock. The configuration of the ring oscillator is adjusted in the second mode by adjusting (i) a power supply value applied to the ring oscillator in the second mode relative to a power supply value applied in the first mode; or (ii) a number of delay line elements that are active in the ring oscillator loop.
摘要翻译： 通常，提供了用于导出具有偏离IC系统时钟的频率的集成电路（IC）时钟信号的方法和装置。 通过以第一模式配置环形振荡器来产生具有偏离系统时钟的频率的偏移时钟，以产生具有期望频率的系统时钟; 以及在第二模式中调整环形振荡器的配置以产生具有偏离系统时钟的频率的偏移时钟。 通过调整（i）相对于在第一模式中施加的电源值，以第二模式施加到环形振荡器的电源值，调节环形振荡器的配置在第二模式中; 或（ii）在环形振荡器回路中有效的多个延迟线元件。
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8.发明授权System and method for maintaining the security of memory contents and computer architecture employing the same 有权用于维护存储器内容的安全性和使用该存储器内容的计算机体系结构的系统和方法公开(公告)号：US08239663B2
公开(公告)日：2012-08-07
申请号：US12475473
申请日：2009-05-30
IPC分类号： G06F21/00
CPC分类号： G06F21/57 , G06F12/1416 , G06F21/74 , G06F21/79
摘要： A secure memory system and a method of maintaining the security of memory contents. One embodiment of the system includes: (1) a security control module configured to transmit a system memory secure mode signal and processor secure mode signal to place the system in a secure mode, (2) a secure memory bridge coupled to the security control and system memory and configured to encrypt and decrypt data associated with the system memory based on a state of the system memory secure mode signal and (3) a boot processor coupled to the security control module and the secure memory bridge and configured to transmit requests to the secure memory bridge in the secure mode and an unsecure mode.
摘要翻译： 一种安全的存储器系统和一种维护存储器内容的安全性的方法。 该系统的一个实施例包括：（1）安全控制模块，被配置为发送系统存储器安全模式信号和处理器安全模式信号以将系统置于安全模式，（2）安全存储器桥耦合到安全控制和 系统存储器并且被配置为基于系统存储器安全模式信号的状态来加密和解密与系统存储器相关联的数据，以及（3）耦合到安全控制模块和安全存储器桥的引导处理器，并且被配置为向 安全模式下的安全内存桥和不安全模式。
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9.发明申请SYSTEM AND METHOD FOR MAINTAINING THE SECURITY OF MEMORY CONTENTS AND COMPUTER ARCHITECTURE EMPLOYING THE SAME 有权用于维护存储器内容安全的系统和方法以及使用其的计算机体系结构公开(公告)号：US20100306519A1
公开(公告)日：2010-12-02
申请号：US12475473
申请日：2009-05-30
CPC分类号： G06F21/57 , G06F12/1416 , G06F21/74 , G06F21/79
摘要： A secure memory system and a method of maintaining the security of memory contents. One embodiment of the system includes: (1) a security control module configured to transmit a system memory secure mode signal and processor secure mode signal to place the system in a secure mode, (2) a secure memory bridge coupled to the security control and system memory and configured to encrypt and decrypt data associated with the system memory based on a state of the system memory secure mode signal and (3) a boot processor coupled to the security control module and the secure memory bridge and configured to transmit requests to the secure memory bridge in the secure mode and an unsecure mode.
摘要翻译： 一种安全的存储器系统和一种维护存储器内容的安全性的方法。 该系统的一个实施例包括：（1）安全控制模块，被配置为发送系统存储器安全模式信号和处理器安全模式信号以将系统置于安全模式，（2）安全存储器桥耦合到安全控制和 系统存储器并且被配置为基于系统存储器安全模式信号的状态来加密和解密与系统存储器相关联的数据，以及（3）耦合到安全控制模块和安全存储器桥的引导处理器，并且被配置为向 安全模式下的安全内存桥和不安全模式。
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10.发明申请公开(公告)号：US20110002186A1
公开(公告)日：2011-01-06
申请号：US12496624
申请日：2009-07-01
IPC分类号： G11C17/18
CPC分类号： G11C17/18
摘要： An electrically programmable fuse, a method of operating the same and an integrated circuit (IC) incorporating the fuse or the method. In one embodiment, the fuse includes: (1) at least one fuse element configured to be programmed with contents and (2) an inhibitor coupled to the at least one fuse element and configured to be activated to inhibit subsequent reprogramming of the at least one fuse element.
摘要翻译： 一种电可编程保险丝，一种操作该保险丝的方法，以及一种结合该保险丝或该方法的集成电路（IC）。 在一个实施例中，熔丝包括：（1）至少一个熔丝元件，其被配置为对内容物进行编程;以及（2）抑制器，其耦合到所述至少一个熔丝元件并被配置为被激活以禁止所述至少一个熔丝元件的后续重新编程 保险丝元件
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