-
1.发明申请Integrated Circuit Performance Enhancement Using On-Chip Adaptive Voltage Scaling 失效使用片上自适应电压调节的集成电路性能增强公开(公告)号：US20100115475A1
公开(公告)日：2010-05-06
申请号：US12261738
申请日：2008-10-30
申请人： Michael S. Buonpane , James D. Chlipala , Richard P. Martin , Richard Muscavage , Scott A. Segan
发明人： Michael S. Buonpane , James D. Chlipala , Richard P. Martin , Richard Muscavage , Scott A. Segan
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , G06F2217/78
摘要： Techniques for enhancing the performance of an IC are provided. A method of enhancing IC performance includes the steps of: associating at least one performance result of at least one performance monitor, formed on the IC, with deterministic combinations of IC performance and a processing parameter, a supply voltage, and/or a temperature of the IC; determining an IC processing characterization of the IC as a function of the performance result for at least one prescribed supply voltage and temperature of the IC, the IC processing characterization being indicative of a type of processing received by the IC during fabrication of the IC; and controlling a voltage supplied to at least a portion of the IC, the voltage being controlled as a function of the IC processing characterization and/or the temperature of the IC so as to satisfy at least one prescribed performance parameter of the IC.
摘要翻译： 提供了用于提高IC性能的技术。 一种提高IC性能的方法包括以下步骤：将形成在IC上的至少一个性能监视器的至少一个性能结果与IC性能与处理参数，电源电压和/或 IC; 根据IC的至少一个规定电源电压和温度的性能结果确定IC的IC处理特征，IC处理特性表示IC在制造IC期间接收的处理类型; 以及控制提供给所述IC的至少一部分的电压，所述电压作为所述IC处理特征和/或所述IC的温度的函数被控制，以满足所述IC的至少一个规定的性能参数。
-
公开(公告)号：US09158359B2
公开(公告)日：2015-10-13
申请号：US13428862
申请日：2012-03-23
申请人： Michael S. Buonpane , James D. Chlipala , Richard P. Martin , Richard Muscavage , Scott A. Segan
发明人： Michael S. Buonpane , James D. Chlipala , Richard P. Martin , Richard Muscavage , Scott A. Segan
CPC分类号： G06F1/3209 , G06F1/325 , G06F1/3296 , Y02D10/172 , Y10T307/406
摘要： An adaptive voltage scaling system includes first and second devices. Each of the first and second devices includes at least one master serial interface port and at least one slave serial interface port. The first device is operatively coupled to a voltage regulator, and the slave serial interface port associated with the second device is operatively coupled to the master serial interface port associated with the first device. The first device controls the voltage regulator based on information obtained from the first and second devices using the master serial interface port associated with the first device and the slave serial interface port associated with the second device. The first and second devices receive voltage from the voltage regulator. A corresponding method and computer-readable medium are also disclosed.
摘要翻译： 自适应电压缩放系统包括第一和第二装置。 第一和第二设备中的每一个包括至少一个主串行接口端口和至少一个从串行接口端口。 第一设备可操作地耦合到电压调节器，并且与第二设备相关联的从串行接口端口可操作地耦合到与第一设备相关联的主串行接口端口。 第一设备使用与第一设备相关联的主串行接口端口和与第二设备相关联的从串行接口端口，基于从第一和第二设备获得的信息来控制电压调节器。 第一和第二器件从电压调节器接收电压。 还公开了相应的方法和计算机可读介质。
-
公开(公告)号：US20130249290A1
公开(公告)日：2013-09-26
申请号：US13428862
申请日：2012-03-23
申请人： Michael S. Buonpane , James D. Chlipala , Richard P. Martin , Richard Muscavage , Scott A. Segan
发明人： Michael S. Buonpane , James D. Chlipala , Richard P. Martin , Richard Muscavage , Scott A. Segan
IPC分类号： H02J1/00
CPC分类号： G06F1/3209 , G06F1/325 , G06F1/3296 , Y02D10/172 , Y10T307/406
摘要： An adaptive voltage scaling system includes first and second devices. Each of the first and second devices includes at least one master serial interface port and at least one slave serial interface port. The first device is operatively coupled to a voltage regulator, and the slave serial interface port associated with the second device is operatively coupled to the master serial interface port associated with the first device. The first device controls the voltage regulator based on information obtained from the first and second devices using the master serial interface port associated with the first device and the slave serial interface port associated with the second device. The first and second devices receive voltage from the voltage regulator. A corresponding method and computer-readable medium are also disclosed.
摘要翻译： 自适应电压缩放系统包括第一和第二装置。 第一和第二设备中的每一个包括至少一个主串行接口端口和至少一个从串行接口端口。 第一设备可操作地耦合到电压调节器，并且与第二设备相关联的从串行接口端口可操作地耦合到与第一设备相关联的主串行接口端口。 第一设备使用与第一设备相关联的主串行接口端口和与第二设备相关联的从串行接口端口，基于从第一和第二设备获得的信息来控制电压调节器。 第一和第二器件从电压调节器接收电压。 还公开了相应的方法和计算机可读介质。
-
4.发明授权Integrated circuit performance enhancement using on-chip adaptive voltage scaling 失效使用片上自适应电压调整的集成电路性能提升公开(公告)号：US08161431B2
公开(公告)日：2012-04-17
申请号：US12261738
申请日：2008-10-30
申请人： Michael S. Buonpane , James D. Chlipala , Richard P. Martin , Richard Muscavage , Scott A. Segan
发明人： Michael S. Buonpane , James D. Chlipala , Richard P. Martin , Richard Muscavage , Scott A. Segan
CPC分类号： G06F17/5063 , G06F2217/78
摘要： Techniques for enhancing the performance of an IC are provided. A method of enhancing IC performance includes the steps of: associating at least one performance result of at least one performance monitor, formed on the IC, with deterministic combinations of IC performance and a processing parameter, a supply voltage, and/or a temperature of the IC; determining an IC processing characterization of the IC as a function of the performance result for at least one prescribed supply voltage and temperature of the IC, the IC processing characterization being indicative of a type of processing received by the IC during fabrication of the IC; and controlling a voltage supplied to at least a portion of the IC, the voltage being controlled as a function of the IC processing characterization and/or the temperature of the IC so as to satisfy at least one prescribed performance parameter of the IC.
摘要翻译： 提供了用于提高IC性能的技术。 一种提高IC性能的方法包括以下步骤：将形成在IC上的至少一个性能监视器的至少一个性能结果与IC性能与处理参数，电源电压和/或 IC; 根据IC的至少一个规定电源电压和温度的性能结果确定IC的IC处理特征，IC处理特性表示IC在制造IC期间接收的处理类型; 以及控制提供给所述IC的至少一部分的电压，所述电压作为所述IC处理特征和/或所述IC的温度的函数被控制，以满足所述IC的至少一个规定的性能参数。
-
5.发明授权Method and apparatus for deriving an integrated circuit (IC) clock with a frequency offset from an IC system clock 有权用于从IC系统时钟频率偏移导出集成电路（IC）时钟的方法和装置公开(公告)号：US07786814B2
公开(公告)日：2010-08-31
申请号：US12199881
申请日：2008-08-28
IPC分类号： H03B5/24
CPC分类号： H03K5/00006 , H03K5/135
摘要： Generally, methods and apparatus are provided for deriving an integrated circuit (IC) clock signal with a frequency that is offset from the IC system clock. An offset clock having a frequency that is offset from a system clock is generated by configuring a ring oscillator in a first mode to generate the system clock having a desired frequency; and adjusting the configuration of the ring oscillator in a second mode to generate the offset clock having the frequency that is offset from the system clock. The configuration of the ring oscillator is adjusted in the second mode by adjusting (i) a power supply value applied to the ring oscillator in the second mode relative to a power supply value applied in the first mode; or (ii) a number of delay line elements that are active in the ring oscillator loop.
摘要翻译： 通常，提供了用于导出具有偏离IC系统时钟的频率的集成电路（IC）时钟信号的方法和装置。 通过以第一模式配置环形振荡器来产生具有偏离系统时钟的频率的偏移时钟，以产生具有期望频率的系统时钟; 以及在第二模式中调整环形振荡器的配置以产生具有偏离系统时钟的频率的偏移时钟。 通过调整（i）相对于在第一模式中施加的电源值，以第二模式施加到环形振荡器的电源值，调节环形振荡器的配置在第二模式中; 或（ii）在环形振荡器回路中有效的多个延迟线元件。
-
6.发明申请METHOD AND APPARATUS FOR DERIVING AN INTEGRATED CIRCUIT (IC) CLOCK WITH A FREQUENCY OFFSET FROM AN IC SYSTEM CLOCK 有权用于从集成电路系统时钟频率偏移传输集成电路（IC）时钟的方法和装置公开(公告)号：US20100052800A1
公开(公告)日：2010-03-04
申请号：US12199881
申请日：2008-08-28
IPC分类号： H03K3/03
CPC分类号： H03K5/00006 , H03K5/135
摘要： Generally, methods and apparatus are provided for deriving an integrated circuit (IC) clock signal with a frequency that is offset from the IC system clock. An offset clock having a frequency that is offset from a system clock is generated by configuring a ring oscillator in a first mode to generate the system clock having a desired frequency; and adjusting the configuration of the ring oscillator in a second mode to generate the offset clock having the frequency that is offset from the system clock. The configuration of the ring oscillator is adjusted in the second mode by adjusting (i) a power supply value applied to the ring oscillator in the second mode relative to a power supply value applied in the first mode; or (ii) a number of delay line elements that are active in the ring oscillator loop.
摘要翻译： 通常，提供了用于导出具有偏离IC系统时钟的频率的集成电路（IC）时钟信号的方法和装置。 通过以第一模式配置环形振荡器来产生具有偏离系统时钟的频率的偏移时钟，以产生具有期望频率的系统时钟; 以及在第二模式中调整环形振荡器的配置以产生具有偏离系统时钟的频率的偏移时钟。 通过调整（i）相对于在第一模式中施加的电源值，以第二模式施加到环形振荡器的电源值，调节环形振荡器的配置在第二模式中; 或（ii）在环形振荡器回路中有效的多个延迟线元件。
-
公开(公告)号：US20110002186A1
公开(公告)日：2011-01-06
申请号：US12496624
申请日：2009-07-01
IPC分类号： G11C17/18
CPC分类号： G11C17/18
摘要： An electrically programmable fuse, a method of operating the same and an integrated circuit (IC) incorporating the fuse or the method. In one embodiment, the fuse includes: (1) at least one fuse element configured to be programmed with contents and (2) an inhibitor coupled to the at least one fuse element and configured to be activated to inhibit subsequent reprogramming of the at least one fuse element.
摘要翻译： 一种电可编程保险丝，一种操作该保险丝的方法，以及一种结合该保险丝或该方法的集成电路（IC）。 在一个实施例中，熔丝包括：（1）至少一个熔丝元件，其被配置为对内容物进行编程;以及（2）抑制器，其耦合到所述至少一个熔丝元件并被配置为被激活以禁止所述至少一个熔丝元件的后续重新编程 保险丝元件
-
公开(公告)号：US20110267096A1
公开(公告)日：2011-11-03
申请号：US12738931
申请日：2009-01-27
IPC分类号： H03K19/00
CPC分类号： H03K19/00 , G01R31/31858 , H03K5/135
摘要： An integrated circuit having a monitor circuit for monitoring timing in a critical path having a target timing margin is disclosed. The monitor circuit has two shift registers, one of which includes a delay element that applies a delay value to a received signal. The inputs to the two shift registers form a signal input node capable of receiving an input signal. The monitor circuit also has a logic gate having an output and at least two inputs, each input connected to a corresponding one of the outputs of the two shift registers. The output of the logic gate indicates whether the target timing margin is satisfied or not satisfied.
摘要翻译： 公开了一种具有用于监视具有目标定时裕度的关键路径中的定时的监视器电路的集成电路。 监视器电路具有两个移位寄存器，其中之一包括向接收信号施加延迟值的延迟元件。 两个移位寄存器的输入形成能够接收输入信号的信号输入节点。 监视器电路还具有一个具有输出和至少两个输入的逻辑门，每个输入连接到两个移位寄存器的相应输出之一。 逻辑门的输出指示目标定时裕度是否满足或不满足。
-
公开(公告)号：US08350589B2
公开(公告)日：2013-01-08
申请号：US12738931
申请日：2009-01-27
CPC分类号： H03K19/00 , G01R31/31858 , H03K5/135
摘要： An integrated circuit having a monitor circuit for monitoring timing in a critical path having a target timing margin is disclosed. The monitor circuit has two shift registers, one of which includes a delay element that applies a delay value to a received signal. The inputs to the two shift registers form a signal input node capable of receiving an input signal. The monitor circuit also has a logic gate having an output and at least two inputs, each input connected to a corresponding one of the outputs of the two shift registers. The output of the logic gate indicates whether the target timing margin is satisfied or not satisfied.
摘要翻译： 公开了一种具有用于监视具有目标定时裕度的关键路径中的定时的监视器电路的集成电路。 监视器电路具有两个移位寄存器，其中之一包括向接收信号施加延迟值的延迟元件。 两个移位寄存器的输入形成能够接收输入信号的信号输入节点。 监视器电路还具有一个具有输出和至少两个输入的逻辑门，每个输入连接到两个移位寄存器的相应输出之一。 逻辑门的输出指示目标定时裕度是否满足或不满足。
-
公开(公告)号：US08315830B2
公开(公告)日：2012-11-20
申请号：US11970597
申请日：2008-01-08
CPC分类号： G06F1/3203 , G06F1/324 , Y02D10/126
摘要： Operational speed of an integrated circuit chip is measured using one or more speed measurement elements, such as ring oscillators, disposed at various regions of the chip. Each speed measuring element can include several ring oscillators, each corresponding to a different technology threshold voltage. The speed measurement data collected from the speed measurement elements can be used to determine on-chip variation (OCV). Circuitry either on the chip itself or, alternatively, external to the chip can adjust a chip operational parameter, such as core voltage or clock speed, in response to the speed measurement data. Speed measurement data can be read out of the chip through JTAG pins or an interface to an external host.
摘要翻译： 使用设置在芯片的各个区域的一个或多个速度测量元件（例如环形振荡器）测量集成电路芯片的操作速度。 每个速度测量元件可以包括几个环形振荡器，每个环形振荡器对应于不同的技术阈值电压。 从速度测量元件收集的速度测量数据可用于确定片上变化（OCV）。 芯片本身或芯片外部的电路可以根据速度测量数据调整芯片工作参数，如核心电压或时钟速度。 速度测量数据可以通过JTAG引脚或与外部主机的接口读出芯片。
-
-
-
-
-
-
-
-
-
搜索结果
25 条记录 (耗时 0.029 秒)
