利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

36 条记录 (耗时 0.033 秒)

    MEMORY CELL PRESETTING FOR IMPROVED MEMORY PERFORMANCE
    6.
    发明申请
    MEMORY CELL PRESETTING FOR IMPROVED MEMORY PERFORMANCE 有权
    用于改善记忆性能的存储单元预置

    公开(公告)号：US20130013860A1

    公开(公告)日：2013-01-10

    申请号：US13619451

    申请日：2012-09-14

    申请人： Michele M. Franceschini ,  Ashish Jagmohan ,  John P. Karidis ,  Luis A. Lastras-Montano ,  Moinuddin K. Qureshi

    发明人： Michele M. Franceschini ,  Ashish Jagmohan ,  John P. Karidis ,  Luis A. Lastras-Montano ,  Moinuddin K. Qureshi

    IPC分类号： G06F12/00 ,  G06F12/08

    CPC分类号： G06F12/00 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0891

    摘要： Memory cell presetting for improved performance including a method for using a computer system to identify a region in a memory. The region includes a plurality of memory cells characterized by a write performance characteristic that has a first expected value when a write operation changes a current state of the memory cells to a desired state of the memory cells and a second expected value when the write operation changes a specified state of the memory cells to the desired state of the memory cells. The second expected value is closer than the first expected value to a desired value of the write performance characteristic. The plurality of memory cells in the region are set to the specified state, and the data is written into the plurality of memory cells responsive to the setting.

    摘要翻译： 用于改进性能的存储单元预设，包括使用计算机系统识别存储器中的区域的方法。 该区域包括多个存储单元，其特征在于当写入操作将存储单元的当前状态改变到存储单元的期望状态时具有第一期望值的写入性能特性，以及当写入操作改变时第二预期值 存储器单元的指定状态到存储器单元的期望状态。 第二期望值比第一期望值更接近写入性能特性的期望值。 区域中的多个存储单元被设置为指定状态，并且响应于该设置将数据写入多个存储单元。

    Memory cell presetting for improved memory performance
    7.
    发明授权
    Memory cell presetting for improved memory performance 有权
    内存单元预置，以提高内存性能

    公开(公告)号：US08874846B2

    公开(公告)日：2014-10-28

    申请号：US13619451

    申请日：2012-09-14

    申请人： Michele M. Franceschini ,  Ashish Jagmohan ,  John P. Karidis ,  Luis A. Lastras-Montano ,  Moinuddin K. Qureshi

    发明人： Michele M. Franceschini ,  Ashish Jagmohan ,  John P. Karidis ,  Luis A. Lastras-Montano ,  Moinuddin K. Qureshi

    IPC分类号： G06F12/00 ,  G06F12/08

    CPC分类号： G06F12/00 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0891

    摘要： Memory cell presetting for improved performance including a method for using a computer system to identify a region in a memory. The region includes a plurality of memory cells characterized by a write performance characteristic that has a first expected value when a write operation changes a current state of the memory cells to a desired state of the memory cells and a second expected value when the write operation changes a specified state of the memory cells to the desired state of the memory cells. The second expected value is closer than the first expected value to a desired value of the write performance characteristic. The plurality of memory cells in the region are set to the specified state, and the data is written into the plurality of memory cells responsive to the setting.

    摘要翻译： 用于改进性能的存储单元预设，包括使用计算机系统识别存储器中的区域的方法。 该区域包括多个存储单元，其特征在于当写入操作将存储单元的当前状态改变到存储单元的期望状态时具有第一期望值的写入性能特性，以及当写入操作改变时第二预期值 存储器单元的指定状态到存储器单元的期望状态。 第二期望值比第一期望值更接近写入性能特性的期望值。 区域中的多个存储单元被设置为指定状态，并且响应于该设置将数据写入多个存储单元。

    ITERATIVE WRITE PAUSING TECHNIQUES TO IMPROVE READ LATENCY OF MEMORY SYSTEMS
    8.
    发明申请
    ITERATIVE WRITE PAUSING TECHNIQUES TO IMPROVE READ LATENCY OF MEMORY SYSTEMS 有权
    迭代写暂停技术来改善读取存储器系统的延迟

    公开(公告)号：US20110026318A1

    公开(公告)日：2011-02-03

    申请号：US12533548

    申请日：2009-07-31

    申请人： Michele M. Franceschini ,  Luis A. Lastras-Montano ,  Moinuddin K. Qureshi ,  Vijayalakshmi Srinivasan

    发明人： Michele M. Franceschini ,  Luis A. Lastras-Montano ,  Moinuddin K. Qureshi ,  Vijayalakshmi Srinivasan

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G06F13/1642 ,  G06F13/161

    摘要： Iterative write pausing techniques to improve read latency of memory systems including memory systems with phase change memory (PCM) devices. A PCM device includes a plurality of memory locations and a mechanism for executing an iterative write to one or more of the memory locations in response to receiving a write command that includes data to be written. The executing includes initiating the iterative write, updating a state of the iterative write, pausing the iterative write including saving the state in response to receiving a pause command, and resuming the iterative write in response to receiving a resume command. The resuming is responsive to the saved state and to the data to be written.

    摘要翻译： 迭代写暂停技术，以提高内存系统（包括具有相变存储器（PCM）设备的存储器系统）的读取延迟。 PCM设备包括多个存储器位置和用于响应于接收到包括要写入的数据的写入命令而执行对一个或多个存储器位置的迭代写入的机制。 执行包括启动迭代写入，更新迭代写入的状态，暂停迭代写入，包括响应于接收到暂停命令而保存状态，以及响应于接收到恢复命令恢复迭代写入。 恢复响应于保存的状态和要写入的数据。