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    ADVANCED MEMORY DEVICE HAVING REDUCED POWER AND IMPROVED PERFORMANCE
    2.
    发明申请
    ADVANCED MEMORY DEVICE HAVING REDUCED POWER AND IMPROVED PERFORMANCE 有权
    具有降低功率的高级存储器件和改进的性能

    公开(公告)号：US20100220536A1

    公开(公告)日：2010-09-02

    申请号：US12394804

    申请日：2009-02-27

    申请人： Paul W. Coteus ,  Daniel M. Dreps ,  Kevin C. Gower ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Kenneth L. Wright

    发明人： Paul W. Coteus ,  Daniel M. Dreps ,  Kevin C. Gower ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Kenneth L. Wright

    IPC分类号： G11C7/00 ,  G11C8/18

    CPC分类号： G11C7/22 ,  G06F13/1689 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/222 ,  G11C8/12 ,  Y02D10/14

    摘要： A memory device including a memory array storing data, a variable delay controller, a passive variable delay circuit and an output driver. The variable delay controller periodically receives delay commands from a first source external to the memory device during operation of the memory device, and outputs delay instruction bits responsive to the received delay commands. The passive variable delay circuit receives a clock from a second source external to the memory device, receives the delay instruction bits from the variable delay controller, generates a delayed clock having a time relation to the received clock as determined by the delay instruction bits, and outputting the delayed clock. The output driver receives the data from the memory array and the delayed clock, and outputs the data at a time responsive to the delayed clock.

    摘要翻译： 一种包括存储数据的存储器阵列，可变延迟控制器，无源可变延迟电路和输出驱动器的存储器件。 可变延迟控制器在存储器件的操作期间周期性地从存储器件外部的第一源接收延迟命令，并且响应于接收的延迟命令而输出延迟指令位。 无源可变延迟电路从存储器件外部的第二源接收时钟，从可变延迟控制器接收延迟指令位，产生与由延迟指令位确定的接收时钟具有时间关系的延迟时钟，以及 输出延迟时钟。 输出驱动器从存储器阵列和延迟时钟接收数据，并且响应于延迟的时钟一次输出数据。

    Advanced memory device having reduced power and improved performance
    3.
    发明授权
    Advanced memory device having reduced power and improved performance 有权
    具有降低的功率和改进的性能的高级存储器件

    公开(公告)号：US07948817B2

    公开(公告)日：2011-05-24

    申请号：US12394804

    申请日：2009-02-27

    申请人： Paul W. Coteus ,  Daniel M. Dreps ,  Kevin C. Gower ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Kenneth L. Wright

    发明人： Paul W. Coteus ,  Daniel M. Dreps ,  Kevin C. Gower ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Kenneth L. Wright

    IPC分类号： G11C7/00

    CPC分类号： G11C7/22 ,  G06F13/1689 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/222 ,  G11C8/12 ,  Y02D10/14

    摘要： A memory device including a memory array storing data, a variable delay controller, a passive variable delay circuit and an output driver. The variable delay controller periodically receives delay commands from a first source external to the memory device during operation of the memory device, and outputs delay instruction bits responsive to the received delay commands. The passive variable delay circuit receives a clock from a second source external to the memory device, receives the delay instruction bits from the variable delay controller, generates a delayed clock having a time relation to the received clock as determined by the delay instruction bits, and outputting the delayed clock. The output driver receives the data from the memory array and the delayed clock, and outputs the data at a time responsive to the delayed clock.

    摘要翻译： 一种包括存储数据的存储器阵列，可变延迟控制器，无源可变延迟电路和输出驱动器的存储器件。 可变延迟控制器在存储器件的操作期间周期性地从存储器件外部的第一源接收延迟命令，并且响应于接收的延迟命令而输出延迟指令位。 无源可变延迟电路从存储器件外部的第二源接收时钟，从可变延迟控制器接收延迟指令位，产生与由延迟指令位确定的接收时钟具有时间关系的延迟时钟，以及 输出延迟时钟。 输出驱动器从存储器阵列和延迟时钟接收数据，并且响应于延迟的时钟一次输出数据。

    System and method for providing error correction and detection in a memory system
    4.
    发明授权
    System and method for providing error correction and detection in a memory system 有权
    在存储器系统中提供纠错和检测的系统和方法

    公开(公告)号：US08055976B2

    公开(公告)日：2011-11-08

    申请号：US11837785

    申请日：2007-08-13

    申请人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Luis A. Lastras-Montano

    发明人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Luis A. Lastras-Montano

    IPC分类号： H03M13/00

    CPC分类号： G06F11/1012 ,  G11C2029/0411

    摘要： A system and method for providing error correction and detection in a memory system. The memory system includes a plurality of memory devices, and error detection and correction logic. The error detection and correction logic includes instructions for generating an error correction code (ECC) word that includes bits from two more of the memory devices and from different memory device transfers.

    摘要翻译： 一种用于在存储器系统中提供纠错和检测的系统和方法。 存储器系统包括多个存储器件，以及错误检测和校正逻辑。 错误检测和校正逻辑包括用于生成包括来自两个以上存储器设备的位和来自不同存储器件传输的位的纠错码（ECC）字的指令。

    SYSTEM AND METHOD FOR PROVIDING ERROR CORRECTION AND DETECTION IN A MEMORY SYSTEM
    5.
    发明申请
    SYSTEM AND METHOD FOR PROVIDING ERROR CORRECTION AND DETECTION IN A MEMORY SYSTEM 有权
    用于在存储器系统中提供错误校正和检测的系统和方法

    公开(公告)号：US20090049365A1

    公开(公告)日：2009-02-19

    申请号：US11837785

    申请日：2007-08-13

    申请人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Luis A. Lastras-Montano

    发明人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Luis A. Lastras-Montano

    IPC分类号： G11C29/00 ,  G06F11/16

    CPC分类号： G06F11/1012 ,  G11C2029/0411

    摘要： A system and method for providing error correction and detection in a memory system. The memory system includes a plurality of memory devices, and error detection and correction logic. The error detection and correction logic includes instructions for generating an error correction code (ECC) word that includes bits from two more of the memory devices and from different memory device transfers.

    摘要翻译： 一种用于在存储器系统中提供纠错和检测的系统和方法。 存储器系统包括多个存储器件，以及错误检测和校正逻辑。 错误检测和校正逻辑包括用于生成包括来自两个以上存储器设备的位和来自不同存储器件传输的位的纠错码（ECC）字的指令。

    MEMORY SYSTEM WITH A PROGRAMMABLE REFRESH CYCLE
    6.
    发明申请
    MEMORY SYSTEM WITH A PROGRAMMABLE REFRESH CYCLE 有权
    具有可编程刷新周期的存储器系统

    公开(公告)号：US20120151131A1

    公开(公告)日：2012-06-14

    申请号：US12963797

    申请日：2010-12-09

    申请人： Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule ,  Vipin Patel

    发明人： Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule ,  Vipin Patel

    IPC分类号： G06F12/00 ,  G11C11/406

    CPC分类号： G11C11/406 ,  G11C2211/4061 ,  G11C2211/4065

    摘要： A memory system with a programmable refresh cycle including a memory device that includes a memory array of memory cells and refresh circuitry that is in communication with the memory array and with a memory controller. The refresh circuitry is configured to receive a refresh command from the memory controller and for refreshing a number of the memory cells in the memory device in response to receiving the refresh command. The number of memory cells refreshed in response to receiving the refresh command is programmable.

    摘要翻译： 一种具有可编程刷新周期的存储器系统，包括存储器件，该存储器件包括与存储器阵列和存储器控制器通信的存储器单元的存储器阵列和刷新电路。 刷新电路被配置为响应于接收到刷新命令从存储器控制器接收刷新命令并且用于刷新存储器件中的多个存储器单元。 响应于接收刷新命令刷新的存储器单元的数量是可编程的。

    Memory system with a programmable refresh cycle
    7.
    发明授权
    Memory system with a programmable refresh cycle 有权
    具有可编程刷新周期的存储系统

    公开(公告)号：US08799566B2

    公开(公告)日：2014-08-05

    申请号：US12963797

    申请日：2010-12-09

    申请人： Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule ,  Vipin Patel

    发明人： Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule ,  Vipin Patel

    IPC分类号： G06F12/00 ,  G11C7/00

    CPC分类号： G11C11/406 ,  G11C2211/4061 ,  G11C2211/4065

    摘要： A memory system with a programmable refresh cycle including a memory device that includes a memory array of memory cells and refresh circuitry that is in communication with the memory array and with a memory controller. The refresh circuitry is configured to receive a refresh command from the memory controller and for refreshing a number of the memory cells in the memory device in response to receiving the refresh command. The number of memory cells refreshed in response to receiving the refresh command is programmable.

    摘要翻译： 一种具有可编程刷新周期的存储器系统，包括存储器件，该存储器件包括与存储器阵列和存储器控制器通信的存储器单元的存储器阵列和刷新电路。 刷新电路被配置为响应于接收到刷新命令从存储器控制器接收刷新命令并且用于刷新存储器件中的多个存储器单元。 响应于接收刷新命令刷新的存储器单元的数量是可编程的。

    Memory interface having extended strobe burst for write timing calibration
    8.
    发明授权
    Memory interface having extended strobe burst for write timing calibration 有权
    存储器接口具有用于写时序校准的扩展选通脉冲串

    公开(公告)号：US08635487B2

    公开(公告)日：2014-01-21

    申请号：US12723843

    申请日：2010-03-15

    申请人： Kevin C. Gower ,  Kyu-hyoun Kim

    发明人： Kevin C. Gower ,  Kyu-hyoun Kim

    IPC分类号： H03M13/00 ,  G06F13/00 ,  G06F3/00 ,  G11C8/00

    CPC分类号： G06F1/04 ,  G06F13/1694 ,  G11C7/1093 ,  G11C2207/2254

    摘要： Methods and systems for calibrating parameters for communication between a controller and a memory device. A memory controller may be configured to calibrate one or more of the write latency and/or the latency window of a memory device such that a data signal and a data strobe signal are received by the memory device within the latency window of the memory device.

    摘要翻译： 用于校准控制器和存储器件之间通信的参数的方法和系统。 存储器控制器可以被配置为校准存储器件的写延迟和/或等待时间窗口中的一个或多个，使得数据信号和数据选通信号在存储器件的延迟窗口内由存储器件接收。

    IMPLEMENTING TIMING ALIGNMENT AND SYNCHRONIZED MEMORY ACTIVITIES OF MULTIPLE MEMORY DEVICES ACCESSED IN PARALLEL
    9.
    发明申请
    IMPLEMENTING TIMING ALIGNMENT AND SYNCHRONIZED MEMORY ACTIVITIES OF MULTIPLE MEMORY DEVICES ACCESSED IN PARALLEL 有权
    实现并行访问的多个存储器件的时序对齐和同步记忆活动

    公开(公告)号：US20130332680A1

    公开(公告)日：2013-12-12

    申请号：US13494280

    申请日：2012-06-12

    申请人： Paul W. Coteus ,  Kyu-hyoun Kim

    发明人： Paul W. Coteus ,  Kyu-hyoun Kim

    IPC分类号： G06F12/00

    CPC分类号： G11C29/26 ,  G06F13/1684 ,  G06F13/1689 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/2602

    摘要： A method and circuit for implementing synchronized memory activities of multiple memory devices being accessed in parallel, and a design structure on which the subject circuit resides are provided. Each memory circuit generates an internal status signal for predefined internal memory activities and provides an output signal coupled to the multiple memory devices. Each memory circuit monitors the generated internal status signal and the output signal of at least one of the multiple memory devices, and responsive to the monitored signals generates a control signal for adjusting operation of its memory activities to synchronize memory activities of the memory devices.

    摘要翻译： 一种用于实现并行访问的多个存储器件的同步存储器活动的方法和电路，以及设置有被摄体电路的设计结构。 每个存储器电路产生用于预定义的内部存储器活动的内部状态信号，并提供耦合到多个存储器件的输出信号。 每个存储器电路监视生成的内部状态信号和多个存储器件中的至少一个的输出信号，并且响应于所监视的信号产生用于调整其存储器活动的操作以控制存储器件的存储器活动的控制信号。

    Multi-use physical architecture
    10.
    发明授权
    Multi-use physical architecture 失效
    多用途物理架构

    公开(公告)号：US08543753B2

    公开(公告)日：2013-09-24

    申请号：US13080799

    申请日：2011-04-06

    申请人： Daniel M. Dreps ,  Kyu-hyoun Kim ,  Michael A. Sorna ,  Glen A. Wiedemeier

    发明人： Daniel M. Dreps ,  Kyu-hyoun Kim ,  Michael A. Sorna ,  Glen A. Wiedemeier

    IPC分类号： G06F1/10 ,  G06F13/38

    CPC分类号： G06F13/385 ,  G06F1/10 ,  G06F13/4072 ,  G11C7/1006 ,  G11C7/1066 ,  G11C7/1093

    摘要： A multi-use physical (PHY) architecture that includes a PHY connection that includes one or more bit lines and that is communicatively coupled to a first processor. The PHY connection is configurable to carry signals between the first processor and a second processor, or between the first processor and a memory. The one or more bit lines are configured to carry signals bi-directionally at a first voltage when the PHY connection is configured to carry signals between the first processor and the memory. The one or more bit lines are configured to carry signals uni-directionally at a second voltage when the PHY connection is configured to carry signals between the first processor and the second processor. The second voltage is different than the first voltage.

    摘要翻译： 一种多用途物理（PHY）架构，其包括包括一个或多个位线并且通信地耦合到第一处理器的PHY连接。 PHY连接可配置为在第一处理器和第二处理器之间或第一处理器和存储器之间传送信号。 一个或多个位线被配置为当PHY连接被配置为在第一处理器和存储器之间传送信号时以双向方式携带信号处于第一电压。 当PHY连接被配置为在第一处理器和第二处理器之间传送信号时，一个或多个位线被配置为以第二电压单向地传送信号。 第二电压不同于第一电压。