公开(公告)号：US20220376693A1

公开(公告)日：2022-11-24

申请号：US17529522

申请日：2021-11-18

Applicant: Microchip Technology Inc.

Inventor： Jonathan W. Greene ,  Marcel Derevlean

IPC: H03K19/17728 ,  H03K19/21 ,  H03K19/17736

Abstract: A logic cell for a programmable logic integrated circuit apparatus includes a K-input lookup table (LUT) circuit having a primary output Y, wherein Y is any function of K inputs, and at least one additional output (F). A carry circuit receives the outputs of the LUT and a carry-in input CI. The carry circuit generates a sum output S and a carry-out output CO. The carry circuit can be configured to provide S=CI and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and CO=CI if Y=q or to select CO from the set {0, 1, F} if Y≠q, where q is a pre-determined value (e.g., such as 0 or 1).

公开(公告)号：US11671099B2

公开(公告)日：2023-06-06

申请号：US17529522

申请日：2021-11-18

Applicant: Microchip Technology Inc.

Inventor： Jonathan W. Greene ,  Marcel Derevlean

IPC: H03K19/17736 ,  H03K19/17728 ,  H03K19/21

CPC classification number: H03K19/17728 ,  H03K19/17736 ,  H03K19/21

Abstract: A logic cell for a programmable logic integrated circuit apparatus includes a K-input lookup table (LUT) circuit having a primary output Y, wherein Y is any function of K inputs, and at least one additional output (F). A carry circuit receives the outputs of the LUT and a carry-in input CI. The carry circuit generates a sum output S and a carry-out output CO. The carry circuit can be configured to provide S=CI and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and CO=CI if Y=q or to select CO from the set {0, 1, F} if Y≠q, where q is a pre-determined value (e.g., such as 0 or 1).