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公开(公告)号：US20140078824A1
公开(公告)日：2014-03-20
申请号：US14029741
申请日：2013-09-17
发明人： David Francis Mietus
IPC分类号： G11C16/26
摘要： Current appearing on a bit-line with no memory cells asserted may be used during a bit-line pre-charge time before a read is performed so as to bias a gate-drain shorted PMOS pull-up device connected between the bit-line and a power supply at a VDD potential. The capacitance connected to the gate of this PMOS pull-up device may be used to “store” the resultant gate-source voltage when the drain is disconnected once the pre-charge time is completed. Once the read operation starts, the current of the PMOS pull-up device that has the “stored” resultant gate-source voltage is re-used as the reference for sensing the state of an asserted memory cell connected to the bit-line during the read operation thereof.
摘要翻译： 在执行读取之前的位线预充电时间期间可能会使用不存在存储单元的位线出现的电流，以便偏置连接在位线与位线之间的栅极 - 漏极短路PMOS上拉器件 VDD电位的电源。 连接到该PMOS上拉装置的栅极的电容可以用于在预充电时间完成时漏极断开时“存储”所得到的栅极 - 源极电压。 一旦读取操作开始，将具有“存储的”合成栅极 - 源极电压的PMOS上拉器件的电流重新用作用于检测连接到位线的断言存储器单元的状态的基准 读取操作。
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公开(公告)号：US09129680B2
公开(公告)日：2015-09-08
申请号：US14029616
申请日：2013-09-17
发明人： David Francis Mietus
摘要： Current appearing on a bit-line with no memory cells asserted may be used during a bit-line pre-charge time before a read is performed so as to bias a gate-drain shorted PMOS pull-up device connected between the bit-line and a power supply at a VDD potential. The capacitance connected to the gate of this PMOS pull-up device may be used to “store” the resultant gate-source voltage when the drain is disconnected once the pre-charge time is completed. Once the read operation starts, the current of the PMOS pull-up device that has the “stored” resultant gate-source voltage and the “stored” resultant gate-source voltage itself are re-used as the references, or multi-reference, for sensing the state of an asserted memory cell connected to the bit-line during the read operation thereof.
摘要翻译： 在执行读取之前的位线预充电时间期间可能会使用不存在存储单元的位线出现的电流，以便偏置连接在位线与位线之间的栅极 - 漏极短路PMOS上拉器件 VDD电位的电源。 连接到该PMOS上拉装置的栅极的电容可以用于在预充电时间完成时漏极断开时“存储”所得到的栅极 - 源极电压。 一旦读操作开始，具有“存储的”合成栅源电压和“存储的”合成栅 - 源电压本身的PMOS上拉器件的电流被重新用作参考或多参考， 用于感测在其读取操作期间连接到位线的被断言的存储器单元的状态。
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公开(公告)号：US20140078831A1
公开(公告)日：2014-03-20
申请号：US14029616
申请日：2013-09-17
发明人： David Francis Mietus
IPC分类号： G11C16/06
摘要： Current appearing on a bit-line with no memory cells asserted may be used during a bit-line pre-charge time before a read is performed so as to bias a gate-drain shorted PMOS pull-up device connected between the bit-line and a power supply at a VDD potential. The capacitance connected to the gate of this PMOS pull-up device may be used to “store” the resultant gate-source voltage when the drain is disconnected once the pre-charge time is completed. Once the read operation starts, the current of the PMOS pull-up device that has the “stored” resultant gate-source voltage and the “stored” resultant gate-source voltage itself are re-used as the references, or multi-reference, for sensing the state of an asserted memory cell connected to the bit-line during the read operation thereof.
摘要翻译： 在执行读取之前的位线预充电时间期间可能会使用不存在存储单元的位线出现的电流，以便偏置连接在位线与位线之间的栅极 - 漏极短路PMOS上拉器件 VDD电位的电源。 连接到该PMOS上拉装置的栅极的电容可以用于在预充电时间完成时漏极断开时“存储”所得到的栅极 - 源极电压。 一旦读操作开始，具有“存储的”合成栅源电压和“存储的”合成栅 - 源电压本身的PMOS上拉器件的电流被重新用作参考或多参考， 用于感测在其读取操作期间连接到位线的被断言的存储器单元的状态。
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公开(公告)号：US09129695B2
公开(公告)日：2015-09-08
申请号：US14029741
申请日：2013-09-17
发明人： David Francis Mietus
摘要： Current appearing on a bit-line with no memory cells asserted may be used during a bit-line pre-charge time before a read is performed so as to bias a gate-drain shorted PMOS pull-up device connected between the bit-line and a power supply at a VDD potential. The capacitance connected to the gate of this PMOS pull-up device may be used to “store” the resultant gate-source voltage when the drain is disconnected once the pre-charge time is completed. Once the read operation starts, the current of the PMOS pull-up device that has the “stored” resultant gate-source voltage is re-used as the reference for sensing the state of an asserted memory cell connected to the bit-line during the read operation thereof.
摘要翻译： 在执行读取之前的位线预充电时间期间可能会使用不存在存储单元的位线出现的电流，以便偏置连接在位线与位线之间的栅极 - 漏极短路PMOS上拉器件 VDD电位的电源。 连接到该PMOS上拉装置的栅极的电容可以用于在预充电时间完成时漏极断开时“存储”所得到的栅极 - 源极电压。 一旦读取操作开始，将具有“存储的”合成栅极 - 源极电压的PMOS上拉器件的电流重新用作用于检测连接到位线的断言存储器单元的状态的基准 读取操作。
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