公开(公告)号：US20130154017A1

公开(公告)日：2013-06-20

申请号：US13709342

申请日：2012-12-10

Applicant: Microchip Technology Incorporated

Inventor： Gregory Dix ,  Harold Kline ,  Rodney Schroeder ,  Daniel J. Grimm

IPC: H01L27/088 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L21/2815 ,  H01L29/42376 ,  H01L29/66477 ,  H01L29/66712 ,  H01L29/7802

Abstract: A field effect transistor has a substrate with an epitaxial layer, base regions extending from a top of the epitaxial layer into the epitaxial layer, an insulation region having side walls and extending between two base regions on top of the substrate; and a polysilicon gate structure covering the insulation region including the side walls, wherein effective gates are formed by a portion of the polysilicon covering side walls above the base region.

Abstract translation: 场效应晶体管具有具有外延层的衬底，从外延层的顶部延伸到外延层中的基极区域，具有侧壁并在衬底顶部的两个基极区域之间延伸的绝缘区域; 以及覆盖包括侧壁的绝缘区域的多晶硅栅极结构，其中有效栅极由位于基极区域上方的多晶硅覆盖侧壁的一部分形成。

公开(公告)号：US20170287834A1

公开(公告)日：2017-10-05

申请号：US15471634

申请日：2017-03-28

Applicant: Microchip Technology Incorporated

Inventor： Dan Grimm ,  Gregory Dix ,  Rodney Schroeder

IPC: H01L23/535 ,  H01L29/06 ,  H01L23/00 ,  H01L27/088 ,  H01L25/00 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/417 ,  H01L25/065

CPC classification number: H01L23/535 ,  H01L21/76829 ,  H01L21/76895 ,  H01L21/823475 ,  H01L23/4824 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/41758 ,  H01L29/78 ,  H01L2224/48137 ,  H01L2225/06506 ,  H01L2225/06582 ,  H01L2924/13091

Abstract: The present disclosure relates to semiconductor devices and the teachings thereof may be embodied in metal oxide semiconductor field effect transistors (MOSFET). Some embodiments may include a power MOSFET with transistor cells, each cell comprising a source and a drain region; a first dielectric layer disposed atop the transistor cells; a silicon rich oxide layer on the first dielectric layer; grooves through the multi-layered dielectric, each groove above a respective source or drain region and filled with a conductive material; a second dielectric layer atop the multi-layered dielectric; openings in the second dielectric layer, each opening exposing a contact area of one of the plurality of grooves; and a metal layer disposed atop the second dielectric layer and filling the openings. The metal layer may form at least one drain metal wire and at least one source metal wire. The at least one drain metal wire may connect two drain regions through respective grooves. The at least one source metal wire may connect two source regions through respective grooves. Each groove has a length extending from the at least one drain metal wire to the at least one source metal wire in an adjacent pair.