公开(公告)号：US20240061587A1

公开(公告)日：2024-02-22

申请号：US17892661

申请日：2022-08-22

Applicant: Micron Technology, Inc.

Inventor： Rakeshkumar Dayabhai Vaghasiya ,  Anilkumar Rameshbhai Sindhi ,  Dhruv Chauhan ,  Mani Raghavendra Aravapalli

IPC: G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/0679 ,  G06F3/0659

Abstract: Methods, systems, and devices for zone write operation techniques are described. A memory system may support zone write operations directly to a multiple-level cell cursor of the memory system. For example, the memory system may close a first zone associated with storing a first type of information from being written with additional information. Based on closing the first zone, the memory system may determine a rate at which the first type of information is written to the memory system. The memory system may receive a command to write second information of the first type to a second zone of the memory system. To write the second information to the second zone, the memory system may write the second information to a cursor configured to store information written to the second zone, and the cursor may be associated with multiple-level memory cells based on the first rate.

公开(公告)号：US20240053900A1

公开(公告)日：2024-02-15

申请号：US17884422

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Rakeshkumar Dayabhai Vaghasiya ,  Anilkumar Rameshbhai Sindhi

IPC: G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/0629 ,  G06F3/0673 ,  G06F3/0659

Abstract: Methods, systems, and devices for sequential write operations using multiple memory dies are described. A memory system may be configured to support write operations that include writing respective subsets of a sequence of data to each first memory die of a set of multiple first memory dies, and then writing the sequence of data to a second memory die (e.g., based on reading the respective subsets of the sequence of data from the set of first memory dies). In some examples, such techniques may be implemented with memory dies having different memory cell storage densities. For example, the set of multiple first memory dies may be operated in accordance with relatively lower storage densities to leverage relatively faster access operations, whereas the second memory die may be operated in accordance with a relatively higher storage density to leverage relatively higher capacity.

公开(公告)号：US12248681B2

公开(公告)日：2025-03-11

申请号：US17884422

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Rakeshkumar Dayabhai Vaghasiya ,  Anilkumar Rameshbhai Sindhi

IPC: G06F3/06

Abstract: Methods, systems, and devices for sequential write operations using multiple memory dies are described. A memory system may be configured to support write operations that include writing respective subsets of a sequence of data to each first memory die of a set of multiple first memory dies, and then writing the sequence of data to a second memory die (e.g., based on reading the respective subsets of the sequence of data from the set of first memory dies). In some examples, such techniques may be implemented with memory dies having different memory cell storage densities. For example, the set of multiple first memory dies may be operated in accordance with relatively lower storage densities to leverage relatively faster access operations, whereas the second memory die may be operated in accordance with a relatively higher storage density to leverage relatively higher capacity.

公开(公告)号：US20240419360A1

公开(公告)日：2024-12-19

申请号：US18744998

申请日：2024-06-17

Applicant: Micron Technology, Inc.

Inventor： Rakeshkumar Dayabhai Vaghasiya ,  Nicola Colella ,  Mani Raghavendra Aravapalli ,  Anilkumar Rameshbhai Sindhi ,  Dhruv Chauhan

IPC: G06F3/06

Abstract: Methods, systems, and devices for data relocation scheme selection for a memory system are described. A system may select, based on a fragmentation characteristic of data associated with a block of addresses, whether to perform a relocation associated with relocating invalid data, or to perform a relocation associated with refraining from relocating invalid data. A relocation associated with relocating invalid data may be selected for relatively more-fragmented data, which may avoid a relatively higher latency or processing load associated with evaluating validity or updating logical-to-physical mapping at a more-granular level. A relocation associated with refraining from relocating invalid data may be selected for relatively less-fragmented data, which may support increasing available space by relocating data to a physical block with available portions that may be written to, taking advantage of a relatively lower latency or processing load associated with evaluating validity or updating logical-to-physical mapping at a less-granular level.

公开(公告)号：US20240168637A1

公开(公告)日：2024-05-23

申请号：US18506873

申请日：2023-11-10

Applicant: Micron Technology, Inc.

Inventor： Nicola Colella ,  Rakeshkumar Dayabhai Vaghasiya ,  Dhruv Chauhan ,  Anilkumar Rameshbhai Sindhi

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and devices for prioritizing refresh operations of a memory system are described. In some instances, a memory system may refresh one or more production state awareness (PSA) blocks at power-on. In some cases, the PSA blocks that are refreshed may have relatively high bit error rates (BERs). For example, PSA blocks with relatively high BERs that are not refreshed may increase the risk of system failure or malfunction. Other PSA blocks may not be refreshed at power-on, and may instead be refreshed at a later time based on one or more criteria in order to prioritize refreshing the PSA blocks having relatively high BERs.