公开(公告)号：US20230062092A1

公开(公告)日：2023-03-02

申请号：US17460984

申请日：2021-08-30

Applicant: Micron Technology, Inc.

Inventor： Hyuck Soo Yang ,  Sau Ha Cheung ,  Richard Beeler ,  Ping Chieh Chiang ,  Hyoung Lee ,  Jaydip Guha ,  Soichi Sugiura

IPC: H01L27/108 ,  H01L29/51

Abstract: A recessed access device comprises a conductive gate in a trench in semiconductor material. A gate insulator extends along sidewalls and around a bottom of the conductive gate between the conductive gate and the semiconductor material. A pair of source/drain regions are in upper portions of the semiconductor material on opposing lateral sides of the trench. A channel region in the semiconductor material below the pair of source/drain regions extends along sidewalls and around a bottom of the trench. The gate insulator comprises a low-k material and a high-k material. The low-k material is characterized by its dielectric constant k being no greater than 4.0. The high-k material is both (a) and (b), where: (a): characterized by its dielectric constant k being greater than 4.0; and (b): comprising SixMyO, where “M” is one or more of Al, metal(s) from Group 2, Group 3, Group 4, Group 5, and the lanthanide series of the periodic table; “x” is 0.999 to 0.6; and “y” is 0.001 to 0.4; the SixMyO being above the low-k material. Other embodiments, including method, are disclosed.

公开(公告)号：US10818667B2

公开(公告)日：2020-10-27

申请号：US16521801

申请日：2019-07-25

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Silvia Borsari ,  Sau Ha Cheung

IPC: H01L27/108 ,  H01L21/02 ,  H01L23/528

Abstract: Some embodiments include an integrated assembly having semiconductor material structures which each have a transistor channel region, and which are over metal-containing structures. Carbon-doped oxide is adjacent regions of each of the semiconductor material structures and sidewalls of the metal-containing structures. Some embodiments include an integrated assembly having pillars of semiconductor material. Each of the pillars has four sidewalls. Two of the four sidewalls of each pillar are gated sidewalls. The other two of the four sidewalls are non-gated sidewalls. Carbon-doped silicon dioxide is adjacent and directly against the non-gated sidewalls. Some embodiments include a method of forming an integrated assembly. Rails of semiconductor material are formed. A layer of carbon-doped silicon dioxide is formed adjacent top surfaces and sidewall surfaces of each of the rails. Trenches are formed which slice the semiconductor material of the rails into pillars. Wordlines are formed within the trenches and along the pillars.

公开(公告)号：US10381352B1

公开(公告)日：2019-08-13

申请号：US15971210

申请日：2018-05-04

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Silvia Borsari ,  Sau Ha Cheung

IPC: H01L27/108 ,  H01L21/02 ,  H01L23/528

Abstract: Some embodiments include an integrated assembly having semiconductor material structures which each have a transistor channel region, and which are over metal-containing structures. Carbon-doped oxide is adjacent regions of each of the semiconductor material structures and sidewalls of the metal-containing structures. Some embodiments include an integrated assembly having pillars of semiconductor material. Each of the pillars has four sidewalls. Two of the four sidewalls of each pillar are gated sidewalls. The other two of the four sidewalls are non-gated sidewalls. Carbon-doped silicon dioxide is adjacent and directly against the non-gated sidewalls. Some embodiments include a method of forming an integrated assembly. Rails of semiconductor material are formed. A layer of carbon-doped silicon dioxide is formed adjacent top surfaces and sidewall surfaces of each of the rails. Trenches are formed which slice the semiconductor material of the rails into pillars. Wordlines are formed within the trenches and along the pillars.

公开(公告)号：US20230397406A1

公开(公告)日：2023-12-07

申请号：US17848107

申请日：2022-06-23

Applicant: Micron Technology, Inc

Inventor： Sau Ha Cheung ,  Soichi Sugiura ,  Jaydip Guha ,  Anthony J. Kanago ,  Richard Beeler

IPC: H01L27/108

CPC classification number: H01L27/10823 ,  H01L27/10876

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a recess formed in a semiconductor material; a dielectric structure formed in the recess; and a control gate for a transistor of a memory cell, the control gate including a first conductive portion formed in the recess and separated from the semiconductor material by a first portion of the dielectric structure, the first dielectric portion including a first dielectric material between the semiconductor material and the second dielectric material, and a second dielectric material between the first dielectric material and the first conductive portion; and the control gate including the second conductive portion formed over the first conductive portion and separated from the semiconductor material by a second portion of the dielectric structure between the semiconductor material and second conductive portion.

公开(公告)号：US20230063549A1

公开(公告)日：2023-03-02

申请号：US17411643

申请日：2021-08-25

Applicant: Micron Technology, Inc.

Inventor： Sau Ha Cheung ,  Soichi Sugiura ,  Jaydip Guha ,  Anthony Kanago ,  Richard Beeler

IPC: H01L29/423 ,  H01L27/108 ,  H01L29/51 ,  H01L29/40

Abstract: A method of forming a recessed access device comprises forming a trench in semiconductor material. Sidewalls and a bottom of the trench are lined with low-k gate-insulator material. The low-k gate-insulator material is characterized by its dielectric constant k being no greater than 4.0. Sacrificial material is formed in a bottom portion of the trench over the low-k gate-insulator material and over the trench bottom. A high-k gate-insulator material is formed in an upper portion of the trench above the sacrificial material and laterally-inward of the low-k gate-insulator material that is in the upper portion of the trench. The high-k gate-insulator material is characterized by its dielectric constant k being greater than 4.0. The sacrificial material is replaced with a conductive gate that has its top above a bottom of the high-k gate-insulator material. A pair of source/drain regions is formed in upper portions of the semiconductor material on opposing lateral sides of the trench. A channel region is in the semiconductor material below the pair of source/drain regions and extends along the trench sidewalls and around the trench bottom. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US11929411B2

公开(公告)日：2024-03-12

申请号：US17411643

申请日：2021-08-25

Applicant: Micron Technology, Inc.

Inventor： Sau Ha Cheung ,  Soichi Sugiura ,  Jaydip Guha ,  Anthony Kanago ,  Richard Beeler

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/51 ,  H10B12/00

CPC classification number: H01L29/4236 ,  H01L29/401 ,  H01L29/42368 ,  H01L29/512 ,  H10B12/053 ,  H10B12/34

Abstract: A method of forming a recessed access device comprises forming a trench in semiconductor material. Sidewalls and a bottom of the trench are lined with low-k gate-insulator material. The low-k gate-insulator material is characterized by its dielectric constant k being no greater than 4.0. Sacrificial material is formed in a bottom portion of the trench over the low-k gate-insulator material and over the trench bottom. A high-k gate-insulator material is formed in an upper portion of the trench above the sacrificial material and laterally-inward of the low-k gate-insulator material that is in the upper portion of the trench. The high-k gate-insulator material is characterized by its dielectric constant k being greater than 4.0. The sacrificial material is replaced with a conductive gate that has its top above a bottom of the high-k gate-insulator material. A pair of source/drain regions is formed in upper portions of the semiconductor material on opposing lateral sides of the trench. A channel region is in the semiconductor material below the pair of source/drain regions and extends along the trench sidewalls and around the trench bottom. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20240074153A1

公开(公告)日：2024-02-29

申请号：US17896039

申请日：2022-08-25

Applicant: Micron Technology, Inc.

Inventor： Daniel Billingsley ,  Jaydip Guha ,  Marko Milojevic ,  Sau Ha Cheung ,  Luca Fumagalli

IPC: H01L27/108 ,  H01B1/02

CPC classification number: H01L27/10823 ,  H01B1/02 ,  H01L27/10876

Abstract: Methods, apparatuses, and systems related to conductive structures are described. An example conductive structure includes a first conductive material including a conductive metal nitride, where the first conductive material has a thickness of at least 0.5 nanometers, and a second conductive material including a conductive metal, where the second conductive material is disposed on a first surface of the first conductive material.