公开(公告)号：US20230352566A1

公开(公告)日：2023-11-02

申请号：US17732028

申请日：2022-04-28

Applicant: Micron Technology, Inc.

Inventor： Bingwu Liu

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/108

CPC classification number: H01L29/66795 ,  H01L29/0649 ,  H01L29/7851 ,  H01L21/76843 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/10805

Abstract: A variety of applications can include devices implementing one or more fin field-effect transistors (FinFETs) with gate oxide thickness that address thicker gate oxide quality with minimum material loss in the fins of the FinFETs for high voltage devices. The gate oxides can be fabricated with thicker oxides than gate oxides of FinFETs used with capacitors in memory cells of memory arrays. These gate oxides can be formed as oxide liners by oxidation with use of a protective liner to maintain uniform composition of material for the fin during FinFET processing.

公开(公告)号：US20240055523A1

公开(公告)日：2024-02-15

申请号：US17883736

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Bingwu Liu ,  Shivani Srivastava ,  Dan Mihai Mocuta

IPC: H01L29/78 ,  H01L27/108 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8234

CPC classification number: H01L29/7851 ,  H01L27/10826 ,  H01L29/66795 ,  H01L29/0847 ,  H01L27/10897 ,  H01L29/66545 ,  H01L21/823431

Abstract: Electronic devices and methods are disclosed, including transistors with thick gate dielectric layers. Selected devices and methods shown include multiple layer gate dielectrics. Selected devices and methods shown include a gate dielectric with a first layer having a first width, and a second layer over the first layer, wherein the second layer has a second width smaller than the first width.

公开(公告)号：US20230335582A1

公开(公告)日：2023-10-19

申请号：US17720122

申请日：2022-04-13

Applicant: Micron Technology, Inc.

Inventor： Shivani Srivastava ,  Toshihiko Miyashita ,  Dan Mihai Mocuta ,  Bingwu Liu ,  Stephen David Snyder

IPC: H01L29/06 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/0642 ,  H01L29/785 ,  H01L27/0886 ,  H01L29/66795

Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include semiconductor devices having two or more fins, the fins separated by one or more inter-fin trenches. An isolation structure is included adjacent to the two or more fins, the isolation structure having a depth greater than the inter-fin trench depth.