公开(公告)号：US20240071832A1

公开(公告)日：2024-02-29

申请号：US17899166

申请日：2022-08-30

Applicant: Micron Technology, Inc

Inventor： Ronald Allen Weimer ,  Toshihiko Miyashita ,  Dan Mihai Mocuta ,  Christopher W. Petz

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/285 ,  H01L27/092 ,  H01L29/08 ,  H01L29/165 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L21/823814 ,  H01L21/02532 ,  H01L21/28518 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/45 ,  H01L29/7848

Abstract: A variety of applications can include apparatus having p-channel metal-oxide-semiconductor (PMOS) transistors and n-channel metal-oxide-semiconductor (NMOS) transistors with different metal silicide contacts. The active area of the NMOS transistor can include a first metal silicide having a first metal element, where the first metal silicide is a vertical lowest portion of a contact for the NMOS. The PMOS transistor can include a stressor source/drain region to a channel region of the PMOS transistor and a second metal silicide directly contacting the stressor source/drain region without containing the first metal element. The process flow to form the PMOS and NMOS transistors can enable making simultaneous contacts by a pre-silicide in the active area of the NMOS transistor, without affecting stressor source/drain regions in the PMOS transistor. The process flow and resulting structures for PMOS transistors and NMOS transistors can be used in various integrated circuits and devices.

公开(公告)号：US20240284663A1

公开(公告)日：2024-08-22

申请号：US18440348

申请日：2024-02-13

Applicant: Micron Technology, Inc.

Inventor： Srinivas Pulugurtha ,  Dan Mihai Mocuta

IPC: H10B12/00 ,  G11C11/4091

CPC classification number: H10B12/50 ,  G11C11/4091

Abstract: A variety of applications can include an apparatus having one or more pairs of transistors sharing a common source region that provide asymmetric transistor devices. The drains of the transistors of a pair sharing a common source region can be structured with the source junction depth being shallower than the drain junction depth of the drain region of at least one of the transistors of the pair. Tilted implantation can be used to extend a drain junction depth beyond the distance of the source junction depth by implanting additional dopants. The extension of the drain junction depth can be accomplished without additional masks being used in processing to dope only a drain region and skip doping on a corresponding source region.

公开(公告)号：US20240064987A1

公开(公告)日：2024-02-22

申请号：US17888650

申请日：2022-08-16

Applicant: Micron Technology, Inc.

Inventor： Toshihiko Miyashita ,  Ronald Allen Weimer ,  Dan Mihai Mocuta

IPC: H01L27/11573 ,  H01L29/45 ,  H01L29/78 ,  H01L27/11529

CPC classification number: H01L27/11573 ,  H01L29/45 ,  H01L29/7843 ,  H01L27/11529

Abstract: Apparatus and methods are disclosed, including transistors, semiconductor devices and systems. Example semiconductor devices and methods include silicide contacts on source/drain regions in different conductivity type transistors. In one example, silicide contacts are different between transistors of different conductivity types.

公开(公告)号：US20240055523A1

公开(公告)日：2024-02-15

申请号：US17883736

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Bingwu Liu ,  Shivani Srivastava ,  Dan Mihai Mocuta

IPC: H01L29/78 ,  H01L27/108 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8234

CPC classification number: H01L29/7851 ,  H01L27/10826 ,  H01L29/66795 ,  H01L29/0847 ,  H01L27/10897 ,  H01L29/66545 ,  H01L21/823431

Abstract: Electronic devices and methods are disclosed, including transistors with thick gate dielectric layers. Selected devices and methods shown include multiple layer gate dielectrics. Selected devices and methods shown include a gate dielectric with a first layer having a first width, and a second layer over the first layer, wherein the second layer has a second width smaller than the first width.

公开(公告)号：US20230335582A1

公开(公告)日：2023-10-19

申请号：US17720122

申请日：2022-04-13

Applicant: Micron Technology, Inc.

Inventor： Shivani Srivastava ,  Toshihiko Miyashita ,  Dan Mihai Mocuta ,  Bingwu Liu ,  Stephen David Snyder

IPC: H01L29/06 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/0642 ,  H01L29/785 ,  H01L27/0886 ,  H01L29/66795

Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include semiconductor devices having two or more fins, the fins separated by one or more inter-fin trenches. An isolation structure is included adjacent to the two or more fins, the isolation structure having a depth greater than the inter-fin trench depth.