公开(公告)号：US20190243788A1

公开(公告)日：2019-08-08

申请号：US16157900

申请日：2018-10-11

Applicant: Micron Technology, Inc.

Inventor： Paul Stonelake ,  Bryan T. Silbermann ,  Frank F. Ross

IPC: G06F13/16 ,  G06F13/42 ,  G06F12/1009 ,  G11C11/406

CPC classification number: G06F13/1689 ,  G06F12/1009 ,  G06F13/1673 ,  G06F13/4243 ,  G11C11/40607

Abstract: A computing system having memory components, including first memory and second memory, wherein the first memory is available to a host system for read and write access over a memory bus during one or more of a first plurality of windows. The computing system further includes a processing device, operatively coupled with the memory components, to: receive, from a driver of the host system, a request regarding a page of data stored in the second memory; responsive to the request, transfer the page from the second memory to a buffer; and write the page from the buffer to the first memory, wherein the page is written to the first memory during at least one of a second plurality of windows corresponding to a refresh timing for the memory bus, and the refresh timing is controlled at the host system.

公开(公告)号：US11030132B2

公开(公告)日：2021-06-08

申请号：US16157900

申请日：2018-10-11

Applicant: Micron Technology, Inc.

Inventor： Paul Stonelake ,  Bryan T. Silbermann ,  Frank F Ross

IPC: G06F13/16 ,  G11C11/406 ,  G06F12/1009 ,  G06F13/42 ,  G06F12/02 ,  G06F13/20

Abstract: A computing system having memory components, including first memory and second memory, wherein the first memory is available to a host system for read and write access over a memory bus during one or more of a first plurality of windows. The computing system further includes a processing device, operatively coupled with the memory components, to: receive, from a driver of the host system, a request regarding a page of data stored in the second memory; responsive to the request, transfer the page from the second memory to a buffer; and write the page from the buffer to the first memory, wherein the page is written to the first memory during at least one of a second plurality of windows corresponding to a refresh timing for the memory bus, and the refresh timing is controlled at the host system.