公开(公告)号：US20230335200A1

公开(公告)日：2023-10-19

申请号：US18130589

申请日：2023-04-04

Applicant: Micron Technology, Inc.

Inventor： Chengbin Sun ,  Carmine Miccoli ,  Violante Moschiano ,  Srinath Venkatesan ,  Walter Di Francesco

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C16/08 ,  G11C16/3404 ,  G11C2207/2254

Abstract: A memory device includes a memory array and control logic, operatively coupled to the memory array, to perform operations including causing a read operation to be initiated with respect to a set of target cells, determining whether the read operation has failed, in response to determining that the read operation has failed, obtaining, for each group of adjacent cells, respective cell state information, assigning, based on the cell state information, each target cell of the set of target cells to a respective state information bin of a set of state information bins, determining whether to initiate auto-calibrated corrective read, in response to determining to initiate auto-calibrated corrective read, performing read level offset calibration to determine a set of calibrated read level offsets, and causing the set of target cells to be read using the set of calibrated read level offsets.