公开(公告)号：US20240268132A1

公开(公告)日：2024-08-08

申请号：US18404657

申请日：2024-01-04

Applicant: Micron Technology, Inc.

Inventor： See Hiong LEOW ,  Hong Wan NG ,  Chin Hui CHONG ,  Ling PAN ,  Kelvin Aik Boo TAN ,  Seng Kim YE

IPC: H10B80/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/06589

Abstract: Some implementations described herein are directed to a semiconductor die package including a stacked die arrangement. The semiconductor die package includes one or more legged support structures between respective overhang portions of the stacked die arrangement and a substrate of the semiconductor die package. The one or more legged support structures may reduce a likelihood of the respective overhang portions deflecting during manufacturing of the semiconductor die package. By reducing the likelihood of the overhang portions deflecting, a quality and reliability of the semiconductor die package may be improved.

公开(公告)号：US20240203842A1

公开(公告)日：2024-06-20

申请号：US18530905

申请日：2023-12-06

Applicant: Micron Technology, Inc.

Inventor： Seng Kim YE ,  Kelvin Aik Boo TAN ,  Hong Wan NG ,  Chin Hui CHONG ,  Ling PAN ,  See Hiong LEOW

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/49565 ,  H01L21/56 ,  H01L23/3114 ,  H01L25/0657

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly includes a circuit substrate comprising a first substrate surface, a second substrate surface arranged opposite to the first substrate surface, and a substrate edge that extends from the first substrate surface to the second substrate surface; a series of holes arranged along the substrate edge of the circuit substrate, wherein each hole of the series of holes extends at least partially from the first substrate surface toward the second substrate surface; at least one die arranged on the first substrate surface; and a package casing disposed over the first substrate surface, wherein the package casing encapsulates the at least one die and the first substrate surface, and wherein the package casing fills each hole of the series of holes.

公开(公告)号：US20240332216A1

公开(公告)日：2024-10-03

申请号：US18606208

申请日：2024-03-15

Applicant: Micron Technology, Inc.

Inventor： See Hiong LEOW ,  Hong Wan NG ,  Kelvin Aik Boo TAN ,  Seng Kim YE ,  Ling PAN ,  Chin Hui CHONG

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/564 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/3128 ,  H01L25/0652 ,  H01L25/18 ,  H10B80/00

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly includes a circuit substrate comprising a first substrate surface and a second substrate surface arranged opposite to the first substrate surface; at least one die arranged on the first substrate surface; a package casing disposed over the first substrate surface, wherein the package casing encapsulates the at least one die and covers at least part of the first substrate surface; a plurality of conductive interconnect structures coupled to the second substrate surface, wherein the plurality of conductive interconnect structures are electrically coupled to the at least one die via the circuit substrate; and at least one molded compound structure arranged on the second substrate surface, wherein the at least one molded compound structure is configured to reduce a coplanarity of the plurality of conductive interconnect structures.

公开(公告)号：US20240128182A1

公开(公告)日：2024-04-18

申请号：US18047411

申请日：2022-10-18

Applicant: Micron Technology, Inc.

Inventor： Chin Hui CHONG ,  Seng Kim YE ,  Hong Wan NG ,  Kelvin Aik Boo TAN

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/48228 ,  H01L2224/48229 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/73257 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a base layer, a dielectric interposer coupled to the base layer and including a first outer surface facing the base layer and an opposing second outer surface facing away from the base layer and spaced apart from the first outer surface in a direction, a first electrical-connection cut-in in the second outer surface that extends, in the direction, toward the first outer surface, and one or more first electrical connections disposed within the first electrical-connection cut-in such that at least a portion of the one or more first electrical connections does not extend, in the direction, beyond the second outer surface.