公开(公告)号：US20240063201A1

公开(公告)日：2024-02-22

申请号：US17820395

申请日：2022-08-17

Applicant: Micron Technology, Inc.

Inventor： See Hiong LEOW ,  Hong Wan NG ,  Seng Kim YE ,  Kelvin Aik Boo TAN ,  Ling PAN

IPC: H01L25/18 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/13147 ,  H01L2924/014 ,  H01L24/13 ,  H01L2224/29199 ,  H01L24/29 ,  H01L2224/29299

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a substrate, a flip chip die electrically coupled to the substrate via a plurality of electrical connections, and a non-conductive film disposed between the flip chip die and the substrate. The non-conductive film may surround the plurality of electrical connections and mechanically couple the flip chip die to the substrate.

公开(公告)号：US20240268132A1

公开(公告)日：2024-08-08

申请号：US18404657

申请日：2024-01-04

Applicant: Micron Technology, Inc.

Inventor： See Hiong LEOW ,  Hong Wan NG ,  Chin Hui CHONG ,  Ling PAN ,  Kelvin Aik Boo TAN ,  Seng Kim YE

IPC: H10B80/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/06589

Abstract: Some implementations described herein are directed to a semiconductor die package including a stacked die arrangement. The semiconductor die package includes one or more legged support structures between respective overhang portions of the stacked die arrangement and a substrate of the semiconductor die package. The one or more legged support structures may reduce a likelihood of the respective overhang portions deflecting during manufacturing of the semiconductor die package. By reducing the likelihood of the overhang portions deflecting, a quality and reliability of the semiconductor die package may be improved.

公开(公告)号：US20240203842A1

公开(公告)日：2024-06-20

申请号：US18530905

申请日：2023-12-06

Applicant: Micron Technology, Inc.

Inventor： Seng Kim YE ,  Kelvin Aik Boo TAN ,  Hong Wan NG ,  Chin Hui CHONG ,  Ling PAN ,  See Hiong LEOW

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/49565 ,  H01L21/56 ,  H01L23/3114 ,  H01L25/0657

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly includes a circuit substrate comprising a first substrate surface, a second substrate surface arranged opposite to the first substrate surface, and a substrate edge that extends from the first substrate surface to the second substrate surface; a series of holes arranged along the substrate edge of the circuit substrate, wherein each hole of the series of holes extends at least partially from the first substrate surface toward the second substrate surface; at least one die arranged on the first substrate surface; and a package casing disposed over the first substrate surface, wherein the package casing encapsulates the at least one die and the first substrate surface, and wherein the package casing fills each hole of the series of holes.

公开(公告)号：US20240162207A1

公开(公告)日：2024-05-16

申请号：US18497637

申请日：2023-10-30

Applicant: Micron Technology, Inc.

Inventor： Kelvin Aik Boo TAN ,  Hong Wan NG ,  See Hiong LEOW ,  Seng Kim YE ,  Ling PAN

IPC: H01L25/16 ,  H01L23/00

CPC classification number: H01L25/165 ,  H01L24/48 ,  H01L25/0652

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor package includes a substrate, a semiconductor die disposed on the substrate, and a passive electronic component disposed on the semiconductor die.

公开(公告)号：US20240063135A1

公开(公告)日：2024-02-22

申请号：US17821272

申请日：2022-08-22

Applicant: Micron Technology, Inc.

Inventor： Hong Wan NG ,  Seng Kim YE ,  Kelvin Aik Boo TAN ,  See Hiong LEOW ,  Ling PAN

IPC: H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L25/065

CPC classification number: H01L23/5387 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/4985 ,  H01L23/49811 ,  H01L21/4853 ,  H01L25/0657 ,  H01L2924/1434 ,  H01L24/48

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly includes a first semiconductor die, a second semiconductor die in a stacked arrangement with the first semiconductor die, and a flexible interposer disposed between the first semiconductor die and the second semiconductor die. The flexible interposer may include a first flexible layer, a second flexible layer, and a conductive trace disposed between the first flexible layer and the second flexible layer. A spacer portion of the flexible interposer may space the first semiconductor die from the second semiconductor die. A connecting portion of the flexible interposer may extend from the spacer portion beyond edges of the first semiconductor die and the second semiconductor die.

公开(公告)号：US20240332216A1

公开(公告)日：2024-10-03

申请号：US18606208

申请日：2024-03-15

Applicant: Micron Technology, Inc.

Inventor： See Hiong LEOW ,  Hong Wan NG ,  Kelvin Aik Boo TAN ,  Seng Kim YE ,  Ling PAN ,  Chin Hui CHONG

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/564 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/3128 ,  H01L25/0652 ,  H01L25/18 ,  H10B80/00

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly includes a circuit substrate comprising a first substrate surface and a second substrate surface arranged opposite to the first substrate surface; at least one die arranged on the first substrate surface; a package casing disposed over the first substrate surface, wherein the package casing encapsulates the at least one die and covers at least part of the first substrate surface; a plurality of conductive interconnect structures coupled to the second substrate surface, wherein the plurality of conductive interconnect structures are electrically coupled to the at least one die via the circuit substrate; and at least one molded compound structure arranged on the second substrate surface, wherein the at least one molded compound structure is configured to reduce a coplanarity of the plurality of conductive interconnect structures.

公开(公告)号：US20240260281A1

公开(公告)日：2024-08-01

申请号：US18406690

申请日：2024-01-08

Applicant: Micron Technology, Inc.

Inventor： Wen Wei LUM ,  Kelvin Aik Boo TAN ,  Seng Kim YE

IPC: H10B80/00 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L21/486 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L25/18 ,  H01L25/50 ,  H01L23/3128 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48235 ,  H01L2924/1436

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a molded memory device may include multiple stacked NAND dies electrically coupled to one another via multiple wire bonds. The molded memory device may include a molded casing surrounding the multiple stacked NAND dies and encapsulating the multiple wire bonds, with the molded casing including a first mold surrounding a first portion of a first NAND die, of the multiple stacked NAND dies, and a second mold partially surrounding a second portion of the first NAND die and each additional NAND die, of the multiple NAND dies. The molded memory device may include multiple copper contacts configured to couple the molded memory device to a substrate associated with a system in package, with the plurality of copper contacts being disposed in the first mold.

公开(公告)号：US20240194630A1

公开(公告)日：2024-06-13

申请号：US18530896

申请日：2023-12-06

Applicant: Micron Technology, Inc.

Inventor： See Hiong LEOW ,  Hong Wan NG ,  Seng Kim YE ,  Kelvin Aik Boo TAN ,  Ling PAN

IPC: H01L23/00 ,  H01L21/48 ,  H01L25/00 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L24/48 ,  H01L21/4853 ,  H01L24/45 ,  H01L24/49 ,  H01L24/85 ,  H01L25/18 ,  H01L25/50 ,  H10B80/00 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48229 ,  H01L2224/49109 ,  H01L2224/85447 ,  H01L2224/85801

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a substrate including multiple first electrical contacts and multiple bondable pillars. In some implementations, each bondable pillar, of the multiple bondable pillars, may be coupled to a corresponding first electrical contact, of the multiple first electrical contacts. The semiconductor device assembly may further include one or more dies coupled to the substrate and including multiple second electrical contacts. In some implementations, the semiconductor device assembly may include multiple wire bonds, with each wire bond, of the multiple wire bonds, bonding a second electrical contact, of the multiple second electrical contacts, to a bondable pillar, of the multiple bondable pillars.

公开(公告)号：US20240162206A1

公开(公告)日：2024-05-16

申请号：US18503560

申请日：2023-11-07

Applicant: Micron Technology, Inc.

Inventor： Seng Kim YE ,  Hong Wan NG ,  Kelvin Aik Boo TAN ,  See Hiong LEOW ,  Ling PAN

IPC: H01L25/16 ,  H01L23/00 ,  H01L25/00 ,  H10B80/00

CPC classification number: H01L25/16 ,  H01L24/05 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L25/50 ,  H10B80/00 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2224/92247 ,  H01L2924/0665

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a substrate and multiple first electrical contacts disposed on the substrate. The semiconductor device assembly may include a load switch coupled to the substrate and including a first outer surface facing the substrate and an opposing second outer surface facing away from the substrate. The load switch may include multiple second electrical contacts disposed on the second outer surface. The semiconductor device assembly may include multiple wire bonds electrically coupling the load switch to the substrate, wherein each wire bond electrically couples a corresponding first electrical contact, of the multiple first electrical contacts, to a corresponding second electrical contact, of the multiple second electrical contacts.

公开(公告)号：US20240128182A1

公开(公告)日：2024-04-18

申请号：US18047411

申请日：2022-10-18

Applicant: Micron Technology, Inc.

Inventor： Chin Hui CHONG ,  Seng Kim YE ,  Hong Wan NG ,  Kelvin Aik Boo TAN

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/48228 ,  H01L2224/48229 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/73257 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a base layer, a dielectric interposer coupled to the base layer and including a first outer surface facing the base layer and an opposing second outer surface facing away from the base layer and spaced apart from the first outer surface in a direction, a first electrical-connection cut-in in the second outer surface that extends, in the direction, toward the first outer surface, and one or more first electrical connections disposed within the first electrical-connection cut-in such that at least a portion of the one or more first electrical connections does not extend, in the direction, beyond the second outer surface.