公开(公告)号：US11928330B2

公开(公告)日：2024-03-12

申请号：US17518154

申请日：2021-11-03

Applicant: Micron Technology, Inc.

Inventor： Shekoufeh Qawami ,  Doyle W. Rivers

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0634 ,  G06F3/0679

Abstract: Techniques to update a trim parameter in non-volatile memory during either a manufacturing stage or a post-manufacturing stage are described. Trim parameters may be stored in a register located within the memory device that is inaccessible by a host device during a normal mode of operation. Post-manufacturing updates to trim parameters by the host device may be feasible by creating registers located within the memory device that are accessible to the host device to provide information regarding trim parameter setting updates. The memory device may read the information from the registers accessible to the host device to update trim parameters stored in the register inaccessible by the host device. In this manner, the host device may not have a direct access to the trim parameters but still be able to provide an update to the trim parameters by updating an entry of the registers accessible by the host device.

公开(公告)号：US11194472B2

公开(公告)日：2021-12-07

申请号：US16848608

申请日：2020-04-14

Applicant: Micron Technology, inc.

Inventor： Shekoufeh Qawami ,  Doyle W. Rivers

IPC: G06F17/00 ,  G06F3/06

Abstract: Techniques to update a trim parameter in non-volatile memory during either a manufacturing stage or a post-manufacturing stage are described. Trim parameters may be stored in a register located within the memory device that is inaccessible by a host device during a normal mode of operation. Post-manufacturing updates to trim parameters by the host device may be feasible by creating registers located within the memory device that are accessible to the host device to provide information regarding trim parameter setting updates. The memory device may read the information from the registers accessible to the host device to update trim parameters stored in the register inaccessible by the host device. In this manner, the host device may not have a direct access to the trim parameters but still be able to provide an update to the trim parameters by updating an entry of the registers accessible by the host device.

公开(公告)号：US20190205030A1

公开(公告)日：2019-07-04

申请号：US15857054

申请日：2017-12-28

Applicant: Micron Technology, Inc.

Inventor： Shekoufeh Qawami ,  Doyle W. Rivers

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0634 ,  G06F3/0679

Abstract: Techniques to update a trim parameter in non-volatile memory during either a manufacturing stage or a post-manufacturing stage are described. Trim parameters may be stored in a register located within the memory device that is inaccessible by a host device during a normal mode of operation. Post-manufacturing updates to trim parameters by the host device may be feasible by creating registers located within the memory device that are accessible to the host device to provide information regarding trim parameter setting updates. The memory device may read the information from the registers accessible to the host device to update trim parameters stored in the register inaccessible by the host device. In this manner, the host device may not have a direct access to the trim parameters but still be able to provide an update to the trim parameters by updating an entry of the registers accessible by the host device.

公开(公告)号：US20220057939A1

公开(公告)日：2022-02-24

申请号：US17518154

申请日：2021-11-03

Applicant: Micron Technology, Inc.

Inventor： Shekoufeh Qawami ,  Doyle W. Rivers

IPC: G06F3/06

Abstract: Techniques to update a trim parameter in non-volatile memory during either a manufacturing stage or a post-manufacturing stage are described. Trim parameters may be stored in a register located within the memory device that is inaccessible by a host device during a normal mode of operation. Post-manufacturing updates to trim parameters by the host device may be feasible by creating registers located within the memory device that are accessible to the host device to provide information regarding trim parameter setting updates. The memory device may read the information from the registers accessible to the host device to update trim parameters stored in the register inaccessible by the host device. In this manner, the host device may not have a direct access to the trim parameters but still be able to provide an update to the trim parameters by updating an entry of the registers accessible by the host device.

公开(公告)号：US10649656B2

公开(公告)日：2020-05-12

申请号：US15857054

申请日：2017-12-28

Applicant: Micron Technology, Inc.

Inventor： Shekoufeh Qawami ,  Doyle W. Rivers

IPC: G11C8/00 ,  G06F3/06

Abstract: Techniques to update a trim parameter in non-volatile memory during either a manufacturing stage or a post-manufacturing stage are described. Trim parameters may be stored in a register located within the memory device that is inaccessible by a host device during a normal mode of operation. Post-manufacturing updates to trim parameters by the host device may be feasible by creating registers located within the memory device that are accessible to the host device to provide information regarding trim parameter setting updates. The memory device may read the information from the registers accessible to the host device to update trim parameters stored in the register inaccessible by the host device. In this manner, the host device may not have a direct access to the trim parameters but still be able to provide an update to the trim parameters by updating an entry of the registers accessible by the host device.

公开(公告)号：US09298545B2

公开(公告)日：2016-03-29

申请号：US14255064

申请日：2014-04-17

Applicant: Micron Technology, Inc.

Inventor： Sampath K. Ratnam ,  Troy D. Larsen ,  Doyle W. Rivers ,  Troy A. Manning ,  Martin L. Culley

IPC: G11C29/00 ,  G06F11/10 ,  G11C11/56 ,  G11C16/04

CPC classification number: G06F11/1068 ,  G06F11/10 ,  G06F11/108 ,  G11C11/5628 ,  G11C16/0483

Abstract: Data protection across multiple memory blocks can include writing a first portion of a codeword in a first location of a first memory block and writing a second portion of the codeword in a second location of a second memory block. The second location of the second memory block can be different than the first location of the first memory block.

Abstract translation: 跨越多个存储器块的数据保护可以包括将码字的第一部分写入第一存储器块的第一位置，并将码字的第二部分写入第二存储器块的第二位置。 第二存储器块的第二位置可以不同于第一存储器块的第一位置。

公开(公告)号：US20200241751A1

公开(公告)日：2020-07-30

申请号：US16848608

申请日：2020-04-14

Applicant: Micron Technology, Inc.

Inventor： Shekoufeh Qawami ,  Doyle W. Rivers

IPC: G06F3/06

Abstract: Techniques to update a trim parameter in non-volatile memory during either a manufacturing stage or a post-manufacturing stage are described. Trim parameters may be stored in a register located within the memory device that is inaccessible by a host device during a normal mode of operation. Post-manufacturing updates to trim parameters by the host device may be feasible by creating registers located within the memory device that are accessible to the host device to provide information regarding trim parameter setting updates. The memory device may read the information from the registers accessible to the host device to update trim parameters stored in the register inaccessible by the host device. In this manner, the host device may not have a direct access to the trim parameters but still be able to provide an update to the trim parameters by updating an entry of the registers accessible by the host device.

公开(公告)号：US20140325316A1

公开(公告)日：2014-10-30

申请号：US14255064

申请日：2014-04-17

Applicant: Micron Technology, Inc.

Inventor： Sampath K. Ratnam ,  Troy D. Larsen ,  Doyle W. Rivers ,  Troy A. Manning ,  Martin L. Culley

IPC: G06F11/10

CPC classification number: G06F11/1068 ,  G06F11/10 ,  G06F11/108 ,  G11C11/5628 ,  G11C16/0483

Abstract: Data protection across multiple memory blocks can include writing a first portion of a codeword in a first location of a first memory block and writing a second portion of the codeword in a second location of a second memory block. The second location can be different than the first location with respect to the second and the first memory blocks.

Abstract translation: 跨越多个存储器块的数据保护可以包括将码字的第一部分写入第一存储器块的第一位置，并将码字的第二部分写入第二存储器块的第二位置。 第二位置可以不同于第二位置和第一存储块的第一位置。