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    SELECTABLE ROW HAMMER MITIGATION
    1.
    发明公开
    SELECTABLE ROW HAMMER MITIGATION 审中-公开

    公开(公告)号：US20240038291A1

    公开(公告)日：2024-02-01

    申请号：US17973726

    申请日：2022-10-26

    Applicant: Micron Technology, Inc.

    Inventor： Edmund J. Gieske ,  Sujeet Ayyapureddi ,  Niccolò Izzo

    IPC: G11C11/4078 ,  G11C11/4096 ,  G11C11/4076

    CPC classification number: G11C11/4078 ,  G11C11/4096 ,  G11C11/4076

    Abstract: An apparatus can include a number of memory devices and a controller coupled to one or more of the number of memory devices. The controller can be configured to determine whether a quantity of row activations directed to a row of the memory devices exceeds a row hammer criterion. The controller can be configured to select, responsive to determining that the row hammer criterion is met, a row hammer mitigation response from a plurality of row hammer mitigation responses available for initiation. The controller can be configured to initiate the selected row hammer mitigation response.

    MEMORY DEVICE SECURITY AND ROW HAMMER MITIGATION
    4.
    发明申请
    MEMORY DEVICE SECURITY AND ROW HAMMER MITIGATION 有权

    公开(公告)号：US20240411466A1

    公开(公告)日：2024-12-12

    申请号：US18808887

    申请日：2024-08-19

    Applicant: Micron Technology, Inc.

    Inventor： Yang Lu ,  Sujeet Ayyapureddi ,  Edmund J. Gieske ,  Cagdas Dirik ,  Ameen D. Akel ,  Elliott C. Cooper-Balis ,  Amitava Majumdar ,  Robert M. Walker ,  Danilo Caraccio

    IPC: G06F3/06

    Abstract: Systems, methods, and apparatus for memory device security and row hammer mitigation are described. A control mechanism may be implemented in a front-end and/or a back-end of a memory sub-system to refresh rows of the memory. A row activation command having a row address at control circuitry of a memory sub-system and incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system may be received. Control circuitry may determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count may be incremented each time the CAM is full. A refresh command to the row address may be issued when a determination is made that the first count is greater than the RHT minus the second count.

    ROW HAMMER MITIGATION USING HIERARCHICAL DETECTORS
    5.
    发明公开
    ROW HAMMER MITIGATION USING HIERARCHICAL DETECTORS 审中-公开

    公开(公告)号：US20230395126A1

    公开(公告)日：2023-12-07

    申请号：US18204786

    申请日：2023-06-01

    Applicant: Micron Technology, Inc.

    Inventor： Edmund J. Gieske ,  Cagdas Dirik ,  Robert M. Walker

    IPC: G11C11/4078 ,  G11C11/406

    CPC classification number: G11C11/4078 ,  G11C11/40618

    Abstract: An apparatus can include a number of memory devices and a controller coupled to one or more of the number of memory devices. The controller can include row hammer detection circuitry configured to receive signaling indicative of a row activation command having a row address, increment a row counter corresponding to the row address stored in a stored in a data structure in a register or storage device, determine whether the incremented row counter is greater than a row hammer threshold, and issue a row hammer mitigation command to mitigate row hammer.

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