公开(公告)号：US20250040121A1

公开(公告)日：2025-01-30

申请号：US18777208

申请日：2024-07-18

Applicant: Micron Technology, Inc.

Inventor： Yuanzhi Ma ,  Scott E. Sills ,  Si-Woo Lee ,  David K. Hwang ,  Yoshitaka Nakamura ,  Yuichi Yokoyama ,  Pavani Vamsi Krishna Nittala ,  Glen H. Walters ,  Gautham Muthusamy ,  Haitao Liu ,  Kamal Karda

IPC: H10B12/00 ,  H10B53/20 ,  H10B53/30

Abstract: Methods, systems, and devices for multi-layer capacitors for three-dimensional memory systems are described. Memory cells of a memory system may include capacitors having dielectric material between multiple interfaces (e.g., concentric interfaces) of a bottom electrode and a top electrode. A bottom electrode may include a first portion wrapping around a portion of a semiconductor material that is contiguous with a channel of a transistor, and a top electrode may include a first portion wrapping around the first portion of the bottom electrode. The bottom electrode may also include a second portion wrapping around the first portion of the top electrode, and the top electrode may also include a second portion wrapping around the second portion of the bottom electrode. The dielectric material may include respective portions between each interface of the bottom electrode and top electrode which, in some examples, may be a contiguous implementation of the dielectric material.