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    SUPPORT PILLARS WITH MULTIPLE, ALTERNATING EPITAXIAL SILICON FOR HORIZONTAL ACCESS DEVICES IN VERTICAL
    2.
    发明公开
    SUPPORT PILLARS WITH MULTIPLE, ALTERNATING EPITAXIAL SILICON FOR HORIZONTAL ACCESS DEVICES IN VERTICAL 审中-公开

    公开(公告)号：US20240098969A1

    公开(公告)日：2024-03-21

    申请号：US17945448

    申请日：2022-09-15

    Applicant: Micron Technology, Inc.

    Inventor： David K. Hwang ,  Yoshitaka Nakamura ,  Scott E. Sills ,  Si-Woo Lee ,  Yuanzhi Ma ,  Glen H. Walters

    IPC: H01L27/108

    CPC classification number: H01L27/10805 ,  H01L27/1085 ,  H01L27/10891

    Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes formed in tiers. And, more particularly, to multiple, alternating silicon germanium (SiGe) and single crystalline silicon (Si) in different thicknesses to form tiers in which to form the horizontal access devices in vertical three-dimensional (3D) memory. The horizontally oriented access devices can have a first source/drain regions and a second source drain regions separated by single crystalline silicon (Si) channel regions. The single crystalline silicon (Si) channel regions can include a dielectric material to provide support structure to the single crystalline channel regions when forming the horizontal access devices in vertical three-dimensional (3D) memory. Horizontally oriented access lines can connect to gate structures opposing the channel regions. Vertical digit lines coupled to the first source/drain regions.

    SELF-ALIGNED CAPACITORS FOR THREE-DIMENSIONAL MEMORY SYSTEMS
    4.
    发明申请
    SELF-ALIGNED CAPACITORS FOR THREE-DIMENSIONAL MEMORY SYSTEMS 有权

    公开(公告)号：US20250159865A1

    公开(公告)日：2025-05-15

    申请号：US18933964

    申请日：2024-10-31

    Applicant: Micron Technology, Inc.

    Inventor： Yuanzhi Ma ,  Scott E. Sills ,  Si-Woo Lee

    IPC: H10B12/00 ,  H10B53/20 ,  H10B53/30

    Abstract: Methods, systems, and devices for self-aligned capacitors for three-dimensional memory systems are described. For example, a capacitor of a memory cell may include multiple interfaces (e.g., concentric interfaces, dielectric interfaces, interfaces at different relative radial positions from an axis of the capacitor) between material portions of a first electrode and a second electrode, each across a respective portion of a dielectric material. A separating dielectric feature may be included between the capacitor and a cell selection transistor of the memory cell, which may support self-alignment of features of the capacitor with features of the cell selection transistor (e.g., self-alignment for fabrication operations associated with forming the capacitor).

    VERTICAL DIGIT LINES WITH ALTERNATING EPITAXIAL SILICON FOR HORIZONTAL ACCESS DEVICES IN 3D MEMORY
    6.
    发明公开
    VERTICAL DIGIT LINES WITH ALTERNATING EPITAXIAL SILICON FOR HORIZONTAL ACCESS DEVICES IN 3D MEMORY 审中-公开

    公开(公告)号：US20240098970A1

    公开(公告)日：2024-03-21

    申请号：US17946925

    申请日：2022-09-16

    Applicant: Micron Technology, Inc.

    Inventor： Scott E. Sills ,  Si-Woo Lee ,  David K. Hwang ,  Yoshitaka Nakamura ,  Yuanzhi Ma ,  Glen H. Walters

    IPC: H01L27/108

    CPC classification number: H01L27/10805 ,  H01L27/10882

    Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source/drain regions and a second source drain regions separated by silicon (Si) channel regions. A digit line having a global digit line (GDL) contact is formed in a trench adjacent to the first source/drain regions. In one example, the digit line is electrically isolated from a neighboring digit line at the bottom of the trench. In another example, the digit line is formed continuously along a bottom surface of trench to form shared digit lines between horizontal access devices, in two separate arrays, on opposing second vertical surfaces. The memory cells have horizontally oriented storage nodes coupled to the second source/drain regions and vertical digit lines coupled to the first source/drain regions.

    SUPPORT STRUCTURE FOR MULTIPLE, ALTERNATING EPITAXIAL SILICON
    8.
    发明公开
    SUPPORT STRUCTURE FOR MULTIPLE, ALTERNATING EPITAXIAL SILICON 审中-公开

    公开(公告)号：US20230397391A1

    公开(公告)日：2023-12-07

    申请号：US17888467

    申请日：2022-08-15

    Applicant: Micron Technology, Inc.

    Inventor： Si-Woo Lee ,  Scott E. Sills ,  David K. Hwang ,  Yoshitaka Nakamura ,  Yuanzhi Ma ,  Glen H. Walters

    IPC: H01L27/108

    CPC classification number: H01L27/10873 ,  H01L27/10805 ,  H01L27/1085 ,  H01L27/10885

    Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source/drain regions and a second source drain regions separated by epitaxially grown, single crystalline silicon (Si) channel regions. A support structure is provided to the epitaxially grown, single crystalline Si. Horizontally oriented access lines connect to gates opposing the channel regions formed fully around every surface of the channel region as gate all around (GAA) structures separated from the channel regions by gate dielectrics. The memory cells have horizontally oriented storage nodes coupled to the second source/drain regions and vertical digit lines coupled to the first source/drain regions.

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