公开(公告)号：US20240098970A1

公开(公告)日：2024-03-21

申请号：US17946925

申请日：2022-09-16

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Si-Woo Lee ,  David K. Hwang ,  Yoshitaka Nakamura ,  Yuanzhi Ma ,  Glen H. Walters

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/10882

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source/drain regions and a second source drain regions separated by silicon (Si) channel regions. A digit line having a global digit line (GDL) contact is formed in a trench adjacent to the first source/drain regions. In one example, the digit line is electrically isolated from a neighboring digit line at the bottom of the trench. In another example, the digit line is formed continuously along a bottom surface of trench to form shared digit lines between horizontal access devices, in two separate arrays, on opposing second vertical surfaces. The memory cells have horizontally oriented storage nodes coupled to the second source/drain regions and vertical digit lines coupled to the first source/drain regions.

公开(公告)号：US20240074141A1

公开(公告)日：2024-02-29

申请号：US17895017

申请日：2022-08-24

Applicant: Micron Technology, Inc.

Inventor： Yoshitaka Nakamura ,  Yuanzhi Ma ,  Scott E. Sills ,  Si-Woo Lee ,  David K. Hwang

IPC: H01L27/108 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/10805 ,  H01L27/1085 ,  H01L27/10873 ,  H01L29/66742 ,  H01L29/78696

Abstract: Methods and devices for a lateral three-dimensional memory device, are described herein. One method includes forming a thin film transistor including a first thermal process having a first range of temperatures, forming a capacitor bottom electrode of a capacitor structure including a second thermal process having a second range of temperature, wherein a maximum temperature in the second range of temperatures is less than a maximum temperature in the first range of temperatures, forming a CMOS structure including a third thermal process having a third range of temperatures, wherein a maximum temperature in the third range of temperatures is less than a maximum temperature in the second range of temperatures, and forming at least one other part of the capacitor structure.

公开(公告)号：US20230397391A1

公开(公告)日：2023-12-07

申请号：US17888467

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Scott E. Sills ,  David K. Hwang ,  Yoshitaka Nakamura ,  Yuanzhi Ma ,  Glen H. Walters

IPC: H01L27/108

CPC classification number: H01L27/10873 ,  H01L27/10805 ,  H01L27/1085 ,  H01L27/10885

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source/drain regions and a second source drain regions separated by epitaxially grown, single crystalline silicon (Si) channel regions. A support structure is provided to the epitaxially grown, single crystalline Si. Horizontally oriented access lines connect to gates opposing the channel regions formed fully around every surface of the channel region as gate all around (GAA) structures separated from the channel regions by gate dielectrics. The memory cells have horizontally oriented storage nodes coupled to the second source/drain regions and vertical digit lines coupled to the first source/drain regions.

公开(公告)号：US20220406899A1

公开(公告)日：2022-12-22

申请号：US17350355

申请日：2021-06-17

Applicant: Micron Technology, Inc.

Inventor： Yoshitaka Nakamura ,  Devesh Dadhich Shreeram ,  Yi Fang Lee ,  Scott E. Sills ,  Jerome A. Imonigie ,  Kaustubh Shrimali

IPC: H01L29/267 ,  H01L27/11507 ,  H01L27/108 ,  H01L23/528 ,  H01L23/532

Abstract: Some embodiments include an integrated assembly containing a first structure which includes one or more transition metals, and containing a second structure over the first structure. The second structure has a first region directly against the first structure and has a second region spaced from the first structure by a gap region. The second structure includes semiconductor material having at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Groups 15 and 16 of the periodic table. An ionic compound is within the gap region. Some embodiments include a method of forming an integrated assembly.

公开(公告)号：US20220059545A1

公开(公告)日：2022-02-24

申请号：US16996527

申请日：2020-08-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Mitsunari Sukekawa ,  Yoshitaka Nakamura

IPC: H01L27/108 ,  H01L21/18 ,  H01L21/311

Abstract: A method including forming a first member having a first portion including a plurality of storage capacitors therein and a second portion surrounding the first portion; forming a second member of a concave shape having a third portion, which corresponds to a lower top surface of the concave shape, including a plurality of access transistors provided correspondingly to the plurality of storage capacitors therein and a fourth portion, which corresponds to an upper top surface of the concave shape, surrounding the third portion; stacking the first member on the second member to physically connect the second and fourth portions and have a gap between the first and third portions; cutting the first member to physically separate the first portion from the second portion; and joining the separated first portion and the third portion with filling the gap therebetween.

公开(公告)号：US20250040121A1

公开(公告)日：2025-01-30

申请号：US18777208

申请日：2024-07-18

Applicant: Micron Technology, Inc.

Inventor： Yuanzhi Ma ,  Scott E. Sills ,  Si-Woo Lee ,  David K. Hwang ,  Yoshitaka Nakamura ,  Yuichi Yokoyama ,  Pavani Vamsi Krishna Nittala ,  Glen H. Walters ,  Gautham Muthusamy ,  Haitao Liu ,  Kamal Karda

IPC: H10B12/00 ,  H10B53/20 ,  H10B53/30

Abstract: Methods, systems, and devices for multi-layer capacitors for three-dimensional memory systems are described. Memory cells of a memory system may include capacitors having dielectric material between multiple interfaces (e.g., concentric interfaces) of a bottom electrode and a top electrode. A bottom electrode may include a first portion wrapping around a portion of a semiconductor material that is contiguous with a channel of a transistor, and a top electrode may include a first portion wrapping around the first portion of the bottom electrode. The bottom electrode may also include a second portion wrapping around the first portion of the top electrode, and the top electrode may also include a second portion wrapping around the second portion of the bottom electrode. The dielectric material may include respective portions between each interface of the bottom electrode and top electrode which, in some examples, may be a contiguous implementation of the dielectric material.

公开(公告)号：US20240282856A1

公开(公告)日：2024-08-22

申请号：US18648180

申请日：2024-04-26

Applicant: Micron Technology, Inc.

Inventor： Yoshitaka Nakamura ,  Yi Fang Lee ,  Jerome A. Imonigie ,  Scott E. Sills ,  Aaron Michael Lowe

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/24 ,  H01L29/417 ,  H01L29/45 ,  H10B12/00

CPC classification number: H01L29/7827 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/24 ,  H01L29/41741 ,  H01L29/45 ,  H10B12/05 ,  H10B12/31

Abstract: Some embodiments include an integrated assembly having an access device between a storage element and a conductive structure. The access device has channel material which includes semiconductor material. The channel material has a first end and an opposing second end, and has a side extending from the first end to the second end. The first end is adjacent the conductive structure, and the second end is adjacent the storage element. Conductive gate material is adjacent the side of the channel material. A first domed metal-containing cap is over the conductive structure and under the channel material and/or a second domed metal-containing cap is over the channel material and under the storage element. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US12015080B2

公开(公告)日：2024-06-18

申请号：US16998877

申请日：2020-08-20

Applicant: Micron Technology, Inc.

Inventor： Yoshitaka Nakamura ,  Yi Fang Lee ,  Jerome A. Imonigie ,  Scott E. Sills ,  Aaron Michael Lowe

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/24 ,  H01L29/417 ,  H01L29/45 ,  H10B12/00

CPC classification number: H01L29/7827 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/24 ,  H01L29/41741 ,  H01L29/45 ,  H10B12/05 ,  H10B12/31

Abstract: Some embodiments include an integrated assembly having an access device between a storage element and a conductive structure. The access device has channel material which includes semiconductor material. The channel material has a first end and an opposing second end, and has a side extending from the first end to the second end. The first end is adjacent the conductive structure, and the second end is adjacent the storage element. Conductive gate material is adjacent the side of the channel material. A first domed metal-containing cap is over the conductive structure and under the channel material and/or a second domed metal-containing cap is over the channel material and under the storage element. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240431095A1

公开(公告)日：2024-12-26

申请号：US18733586

申请日：2024-06-04

Applicant: Micron Technology, Inc.

Inventor： Yoshitaka Nakamura ,  Ashwin Panday ,  Iche Huang ,  Richard Beeler ,  Dojun Kim ,  Lane T. Cunningham ,  Adriel Jebin Jacob Jebaraj ,  Scott E. Sills

IPC: H10B12/00

Abstract: Methods, apparatuses, and systems related to a three-dimensional semiconductor device having a doped liner at least disposed between a capacitor and an access device. The doped liner may be configured to provide dopants that diffuse into a semiconductor path of the access device and improve an electrical connection between the access device and the capacitor.

公开(公告)号：US11848360B2

公开(公告)日：2023-12-19

申请号：US17350355

申请日：2021-06-17

Applicant: Micron Technology, Inc.

Inventor： Yoshitaka Nakamura ,  Devesh Dadhich Shreeram ,  Yi Fang Lee ,  Scott E. Sills ,  Jerome A. Imonigie ,  Kaustubh Shrimali

IPC: H01L29/267 ,  H10B12/00 ,  H01L23/528 ,  H10B53/30

CPC classification number: H01L29/267 ,  H01L23/5283 ,  H10B12/033 ,  H10B12/05 ,  H10B12/315 ,  H10B12/482 ,  H10B53/30

Abstract: Some embodiments include an integrated assembly containing a first structure which includes one or more transition metals, and containing a second structure over the first structure. The second structure has a first region directly against the first structure and has a second region spaced from the first structure by a gap region. The second structure includes semiconductor material having at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Groups 15 and 16 of the periodic table. An ionic compound is within the gap region. Some embodiments include a method of forming an integrated assembly.