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    FERROELECTRIC MEMORY ARRAYS WITH LOW PERMITTIVITY DIELECTRIC BARRIERS
    2.
    发明公开
    FERROELECTRIC MEMORY ARRAYS WITH LOW PERMITTIVITY DIELECTRIC BARRIERS 审中-公开

    公开(公告)号：US20230397428A1

    公开(公告)日：2023-12-07

    申请号：US18203886

    申请日：2023-05-31

    Applicant: Micron Technology, Inc.

    Inventor： Giorgio Servalli ,  Marcello Mariani ,  Kamal Karda

    IPC: H10B51/30

    CPC classification number: H10B51/30

    Abstract: Methods, systems, and devices for ferroelectric memory arrays with low permittivity dielectric barriers are described. In some cases, a manufacturing process to manufacture a memory array may include depositing a dielectric barrier between respective bottom electrodes of a pair of adjacent memory cells of the array. For example, the manufacturing process may include depositing a film of dielectric material over rows of bottom electrodes formed on a set of dielectric walls to at least partially fill space between adjacent bottom electrodes. Alternatively, the manufacturing process may include depositing a film of dielectric material into a set of cavities of the memory array, each cavity having a set of bottom electrodes formed on sidewalls of the cavity. Subsequently, a portion of the dielectric material may be removed to expose surfaces of the bottom electrodes, leaving behind a set of dielectric barriers between adjacent bottom electrodes.

    NAND STRUCTURES WITH POLARIZED MATERIALS
    4.
    发明公开
    NAND STRUCTURES WITH POLARIZED MATERIALS 审中-公开

    公开(公告)号：US20230371264A1

    公开(公告)日：2023-11-16

    申请号：US17662982

    申请日：2022-05-11

    Applicant: Micron Technology, Inc.

    Inventor： Albert Fayrushin ,  Kamal Karda ,  Gianpietro Carnevale ,  Aurelio Giancarlo Mauri

    IPC: H01L27/11597 ,  H01L27/1159

    CPC classification number: H01L27/11597 ,  H01L27/1159

    Abstract: Methods, systems, and devices for NAND structures with polarized materials are described. A memory device may include a polarized dielectric material located relatively near to a channel, which may reduce interference between cells. The polarized dielectric material may include a dielectric material with a fixed polarity and having a first surface with a negative polarity oriented towards the channel. The negative polarity of the polarized dielectric material may affect an electron distribution of the channel by shifting the electron distribution closer to an associated charge trapping material. The shifted electron distribution may reduce an effect of an electric field of any aggressor cells of the memory device on one or more victim cells, by creating a more uniform channel electron distribution and increasing gate control relative to a channel without the effects of the polarized dielectric material.

    NAND structures with polarized materials
    6.
    发明授权
    NAND structures with polarized materials 有权

    公开(公告)号：US12279434B2

    公开(公告)日：2025-04-15

    申请号：US17662982

    申请日：2022-05-11

    Applicant: Micron Technology, Inc.

    Inventor： Albert Fayrushin ,  Kamal Karda ,  Gianpietro Carnevale ,  Aurelio Giancarlo Mauri

    IPC: H10B51/20 ,  H10B51/30

    Abstract: Methods, systems, and devices for NAND structures with polarized materials are described. A memory device may include a polarized dielectric material located relatively near to a channel, which may reduce interference between cells. The polarized dielectric material may include a dielectric material with a fixed polarity and having a first surface with a negative polarity oriented towards the channel. The negative polarity of the polarized dielectric material may affect an electron distribution of the channel by shifting the electron distribution closer to an associated charge trapping material. The shifted electron distribution may reduce an effect of an electric field of any aggressor cells of the memory device on one or more victim cells, by creating a more uniform channel electron distribution and increasing gate control relative to a channel without the effects of the polarized dielectric material.

    DOPING TECHNIQUES FOR MEMORY CELL SELECTION TRANSISTORS
    7.
    发明申请
    DOPING TECHNIQUES FOR MEMORY CELL SELECTION TRANSISTORS 有权

    公开(公告)号：US20250040130A1

    公开(公告)日：2025-01-30

    申请号：US18773001

    申请日：2024-07-15

    Applicant: Micron Technology, Inc.

    Inventor： Kamal Karda ,  Haitao Liu ,  Scott E. Sills ,  Si-Woo Lee

    IPC: H10B12/00

    Abstract: Methods, systems, and devices for doping of memory cell selection transistors are described. Cell selection transistors of an array of memory cells may each include a semiconductor channel that is doped at a middle portion of the channel, which may support a deselection voltage for relatively high channel resistance that is relatively closer to or equal to a ground voltage than other transistor configurations. The semiconductor channels may include a p-type doping (e.g., using a configured concentration of boron) at a middle portion of the channels that is between end portions that are doped with an n-type doping (e.g., using phosphorous, arsenic, or a combination thereof, among other examples of n-type doping). In some implementations, undoped regions may be included between the n-type doped portions and the p-type doped portions. Such techniques may be implemented in horizontal cell selection transistors formed over a substrate, including for three-dimensional memory arrays.

    THREE-DIMENSIONAL NOR MEMORY DEVICE FOR MULTIPLY-ACCUMULATE OPERATIONS
    8.
    发明申请
    THREE-DIMENSIONAL NOR MEMORY DEVICE FOR MULTIPLY-ACCUMULATE OPERATIONS 有权

    公开(公告)号：US20250029659A1

    公开(公告)日：2025-01-23

    申请号：US18741633

    申请日：2024-06-12

    Applicant: Micron Technology, Inc.

    Inventor： Kamal Karda ,  Hernan Castro

    IPC: G11C16/08 ,  G11C5/06 ,  G11C16/04

    Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication using memory cells. In one approach, a memory cell array has memory cells stacked vertically above a semiconductor substrate. Each memory cell stores a weight. Local digit lines connect to terminals of the memory cells. The local digit lines extend vertically above the substrate. Select transistors connect to the local digit lines. Select lines control the select transistors, and are used to encode an input pattern to multiply by the stored weights. Accumulation circuitry sums output currents from the memory cells. In one example, each memory cell is formed using a transistor that includes a semiconductor layer to provide a horizontal channel. A gate layer (e.g., a gate stack layer) wraps around a circumference of the semiconductor layer. Wordlines apply gate voltages to the transistors. Each wordline has a respective portion that wraps around a circumference of the gate layer of each transistor.

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