公开(公告)号：US20240098969A1

公开(公告)日：2024-03-21

申请号：US17945448

申请日：2022-09-15

Applicant: Micron Technology, Inc.

Inventor： David K. Hwang ,  Yoshitaka Nakamura ,  Scott E. Sills ,  Si-Woo Lee ,  Yuanzhi Ma ,  Glen H. Walters

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/1085 ,  H01L27/10891

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes formed in tiers. And, more particularly, to multiple, alternating silicon germanium (SiGe) and single crystalline silicon (Si) in different thicknesses to form tiers in which to form the horizontal access devices in vertical three-dimensional (3D) memory. The horizontally oriented access devices can have a first source/drain regions and a second source drain regions separated by single crystalline silicon (Si) channel regions. The single crystalline silicon (Si) channel regions can include a dielectric material to provide support structure to the single crystalline channel regions when forming the horizontal access devices in vertical three-dimensional (3D) memory. Horizontally oriented access lines can connect to gate structures opposing the channel regions. Vertical digit lines coupled to the first source/drain regions.

公开(公告)号：US20240064962A1

公开(公告)日：2024-02-22

申请号：US17889384

申请日：2022-08-16

Applicant: Micron Technology, Inc.

Inventor： David K. Hwang ,  Litao Yang

IPC: H01L27/108 ,  H01L29/423 ,  H01L29/08 ,  H01L29/167

CPC classification number: H01L27/10811 ,  H01L27/10873 ,  H01L29/42392 ,  H01L29/0847 ,  H01L29/167

Abstract: Systems, methods and apparatus are provided for three-dimensional memory devices, including an array of vertically stacked memory cells having: access devices each respectively including: a semiconductor material comprising a first source/drain region and a second source/drain region separated by a respective channel region, and a respective gate opposing the respective channel region and separated therefrom by a respective gate dielectric; a respective first doped dielectric material adjacent to the respective gate and the respective semiconductor material; and a respective second doped dielectric material adjacent to the respective gate and the respective semiconductor material, wherein the respective second doped dielectric material is opposite to the respective first doped dielectric material relative to the respective gate; storage nodes electrically coupled to the respective second source/drain regions of the access devices.

公开(公告)号：US20230397390A1

公开(公告)日：2023-12-07

申请号：US17888460

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： David K. Hwang ,  John F. Kaeding ,  Matthew S. Thorum ,  Yuanzhi Ma ,  Scott E. Sills ,  Si-Woo Lee ,  Yoshitaka Nakamura ,  Glen H. Walters

IPC: H01L27/108 ,  G11C5/06

CPC classification number: H01L27/10873 ,  H01L27/1085 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10805 ,  G11C5/063

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes formed in tiers. And, more particularly, to multiple, alternating epitaxially grown silicon germanium (SiGe) and single crystalline silicon (Si) in different thicknesses to form tiers in which to form the horizontal access devices in vertical three dimensional (3D) memory. The horizontally oriented access devices can have a first source/drain regions and a second source drain regions separated by epitaxially grown, single crystalline silicon (Si) channel regions. Horizontally oriented access lines can connect to gate all around (GAA) structures opposing the channel regions. Vertical digit lines coupled to the first source/drain regions.

公开(公告)号：US20220068932A1

公开(公告)日：2022-03-03

申请号：US17376077

申请日：2021-07-14

Applicant: Micron Technology, Inc.

Inventor： David K. Hwang ,  Richard J. Hill ,  Gurtej S. Sandhu

IPC: H01L27/108 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66

Abstract: Some embodiments include an integrated assembly having first conductive structures extending along a first direction. Spaced-apart upwardly-opening container-shapes are over the first conductive structures. Each of the container-shapes has a first sidewall region, a second sidewall region, and a bottom region extending from the first sidewall region to the second sidewall region. Each of the first and second sidewall regions includes a lower source/drain region, an upper source/drain region, and a channel region between the upper and lower source/drain regions. The lower source/drain regions are electrically coupled with the first conductive structures. Second conductive structures extend along a second direction which crosses the first direction. The second conductive structures have gate regions operatively adjacent the channel regions. Storage elements are electrically coupled with the upper source/drain regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20250040121A1

公开(公告)日：2025-01-30

申请号：US18777208

申请日：2024-07-18

Applicant: Micron Technology, Inc.

Inventor： Yuanzhi Ma ,  Scott E. Sills ,  Si-Woo Lee ,  David K. Hwang ,  Yoshitaka Nakamura ,  Yuichi Yokoyama ,  Pavani Vamsi Krishna Nittala ,  Glen H. Walters ,  Gautham Muthusamy ,  Haitao Liu ,  Kamal Karda

IPC: H10B12/00 ,  H10B53/20 ,  H10B53/30

Abstract: Methods, systems, and devices for multi-layer capacitors for three-dimensional memory systems are described. Memory cells of a memory system may include capacitors having dielectric material between multiple interfaces (e.g., concentric interfaces) of a bottom electrode and a top electrode. A bottom electrode may include a first portion wrapping around a portion of a semiconductor material that is contiguous with a channel of a transistor, and a top electrode may include a first portion wrapping around the first portion of the bottom electrode. The bottom electrode may also include a second portion wrapping around the first portion of the top electrode, and the top electrode may also include a second portion wrapping around the second portion of the bottom electrode. The dielectric material may include respective portions between each interface of the bottom electrode and top electrode which, in some examples, may be a contiguous implementation of the dielectric material.

公开(公告)号：US20240121943A1

公开(公告)日：2024-04-11

申请号：US18545180

申请日：2023-12-19

Applicant: Micron Technology, Inc.

Inventor： David K. Hwang ,  Richard J. Hill ,  Gurtej S. Sandhu

IPC: H10B12/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H10B12/315 ,  H01L29/0684 ,  H01L29/42356 ,  H01L29/66666 ,  H01L29/7827 ,  H10B12/0335 ,  H10B12/482 ,  H10B12/488

Abstract: Some embodiments include an integrated assembly having first conductive structures extending along a first direction. Spaced-apart upwardly-opening container-shapes are over the first conductive structures. Each of the container-shapes has a first sidewall region, a second sidewall region, and a bottom region extending from the first sidewall region to the second sidewall region. Each of the first and second sidewall regions includes a lower source/drain region, an upper source/drain region, and a channel region between the upper and lower source/drain regions. The lower source/drain regions are electrically coupled with the first conductive structures. Second conductive structures extend along a second direction which crosses the first direction. The second conductive structures have gate regions operatively adjacent the channel regions. Storage elements are electrically coupled with the upper source/drain regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11889680B2

公开(公告)日：2024-01-30

申请号：US17376077

申请日：2021-07-14

Applicant: Micron Technology, Inc.

Inventor： David K. Hwang ,  Richard J. Hill ,  Gurtej S. Sandhu

IPC: H10B12/00 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

CPC classification number: H10B12/315 ,  H01L29/0684 ,  H01L29/42356 ,  H01L29/66666 ,  H01L29/7827 ,  H10B12/0335 ,  H10B12/482 ,  H10B12/488

Abstract: Some embodiments include an integrated assembly having first conductive structures extending along a first direction. Spaced-apart upwardly-opening container-shapes are over the first conductive structures. Each of the container-shapes has a first sidewall region, a second sidewall region, and a bottom region extending from the first sidewall region to the second sidewall region. Each of the first and second sidewall regions includes a lower source/drain region, an upper source/drain region, and a channel region between the upper and lower source/drain regions. The lower source/drain regions are electrically coupled with the first conductive structures. Second conductive structures extend along a second direction which crosses the first direction. The second conductive structures have gate regions operatively adjacent the channel regions. Storage elements are electrically coupled with the upper source/drain regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11777036B2

公开(公告)日：2023-10-03

申请号：US17005054

申请日：2020-08-27

Applicant: Micron Technology, Inc.

Inventor： David K. Hwang ,  Richard J. Hill ,  Gurtej S. Sandhu

IPC: H01L29/24 ,  H01L29/786 ,  H01L29/423 ,  H01L27/12 ,  G11C11/408 ,  H01L29/16 ,  G11C11/22 ,  G11C11/4091

CPC classification number: H01L29/78618 ,  H01L27/127 ,  H01L27/1214 ,  H01L27/1255 ,  H01L27/1262 ,  H01L29/42384 ,  H01L29/78642 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2273 ,  G11C11/4085 ,  G11C11/4091 ,  H01L27/1225 ,  H01L29/1606 ,  H01L29/24 ,  H01L29/78696

Abstract: Some embodiments include an integrated assembly having an upwardly-extending structure with a sidewall surface. Two-dimensional-material extends along the sidewall surface. First electrostatic-doping-material is adjacent a lower region of the two-dimensional-material, insulative material is adjacent a central region of the two-dimensional-material, and second electrostatic-doping-material is adjacent an upper region of the two-dimensional-material. A conductive-gate-structure is over the first electrostatic-doping-material and adjacent to the insulative material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11670707B2

公开(公告)日：2023-06-06

申请号：US17840250

申请日：2022-06-14

Applicant: Micron Technology, Inc.

Inventor： David K. Hwang ,  John F. Kaeding ,  Richard J. Hill ,  Scott E. Sills

IPC: H01L21/00 ,  H01L29/76 ,  H01L29/66 ,  H01L27/11509 ,  H01L27/108 ,  H01L29/16 ,  H01L29/26 ,  H01L29/786 ,  H01L21/02 ,  H01L27/11507

CPC classification number: H01L29/7606 ,  H01L21/02521 ,  H01L21/02527 ,  H01L21/02568 ,  H01L27/10808 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10897 ,  H01L27/11507 ,  H01L27/11509 ,  H01L29/1606 ,  H01L29/26 ,  H01L29/66045 ,  H01L29/66969 ,  H01L29/78642 ,  H01L29/78696

Abstract: Some embodiments include an integrated assembly having a conductive structure, an annular structure extending through the conductive structure, and an active-material-structure lining an interior periphery of the annular structure. The annular structure includes dielectric material. The active-material-structure includes two-dimensional-material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220310831A1

公开(公告)日：2022-09-29

申请号：US17840250

申请日：2022-06-14

Applicant: Micron Technology, Inc.

Inventor： David K. Hwang ,  John F. Kaeding ,  Richard J. Hill ,  Scott E. Sills

IPC: H01L29/76 ,  H01L29/66 ,  H01L27/11509 ,  H01L27/108 ,  H01L29/16 ,  H01L29/26 ,  H01L29/786 ,  H01L21/02 ,  H01L27/11507

Abstract: Some embodiments include an integrated assembly having a conductive structure, an annular structure extending through the conductive structure, and an active-material-structure lining an interior periphery of the annular structure. The annular structure includes dielectric material. The active-material-structure includes two-dimensional-material. Some embodiments include methods of forming integrated assemblies.