公开(公告)号：US20220357791A1

公开(公告)日：2022-11-10

申请号：US17870696

申请日：2022-07-21

Applicant: Micron Technology, Inc.

Inventor： Greg Blodgett ,  Daniele Balluchi ,  Danilo Caraccio ,  Graziano Mirichigni

IPC: G06F1/3234 ,  G06F13/16 ,  G11C5/14

Abstract: The present disclosure includes apparatuses and methods for providing energy information to memory. An embodiment includes determining, by a host, that a charge level of an energy source coupled to the host has reached or exceeded a threshold value, and transmitting, from the host to a memory device coupled to the host, signaling indicative of an energy mode for the memory device, wherein the signaling is transmitted based at least in part on determining that the charge level of the energy source has reached or exceeded the threshold.

公开(公告)号：US20200064903A1

公开(公告)日：2020-02-27

申请号：US16666975

申请日：2019-10-29

Applicant: Micron Technology, Inc.

Inventor： Greg Blodgett ,  Daniele Balluchi ,  Danilo Caraccio ,  Graziano Mirichigni

IPC: G06F1/3234 ,  G06F13/16 ,  G11C5/14

Abstract: The present disclosure includes apparatuses and methods for providing energy information to memory. An embodiment includes determining, by a host, that a charge level of an energy source coupled to the host has reached or exceeded a threshold value, and transmitting, from the host to a memory device coupled to the host, signaling indicative of an energy mode for the memory device, wherein the signaling is transmitted based at least in part on determining that the charge level of the energy source has reached or exceeded the threshold.

公开(公告)号：US20180336146A1

公开(公告)日：2018-11-22

申请号：US15815209

申请日：2017-11-16

Applicant: Micron Technology, Inc.

Inventor： Greg Blodgett ,  Daniele Balluchi ,  Danilo Caraccio ,  Graziano Mirichigni

IPC: G06F13/16 ,  G11C5/14

Abstract: The present disclosure includes apparatuses and methods for providing energy information to memory. An embodiment includes determining, by a host, that a charge level of an energy source coupled to the host has reached or exceeded a threshold value, and transmitting, from the host to a memory device coupled to the host, signaling indicative of an energy mode for the memory device, wherein the signaling is transmitted based at least in part on determining that the charge level of the energy source has reached or exceeded the threshold.

公开(公告)号：US20130272075A1

公开(公告)日：2013-10-17

申请号：US13911863

申请日：2013-06-06

Applicant: Micron Technology, Inc.

Inventor： Greg Blodgett

IPC: G11C17/16

CPC classification number: G11C17/16 ,  G11C29/787 ,  G11C29/812

Abstract: A memory chip design methodology is disclosed wherein fuse banks on the memory chip may be implemented without enable fuses. A fuse bank may be enabled by using one or more least significant bits (LSBs) in the memory address stored in the fuse bank, thereby avoiding the need for a separate enable fuse. A reduction in the number of fuses results in space savings on the memory chip real estate and also savings in power consumption because of fewer fuses to be blown and read. With reduced fuse count, the yield of the memory chip's die may also be improved because of less number of defective fuses or failed fuse blows. The use of effective default state inversion for address fuses may further reduce the average number of fuses that need to be blown to repair a given non-redundant memory address. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract translation: 公开了一种存储器芯片设计方法，其中可以在不使能熔丝的情况下实现存储器芯片上的熔丝组。 可以通过使用存储在熔丝组中的存储器地址中的一个或多个最低有效位（LSB）来使能熔丝组，从而避免需要单独的使能熔丝。 保险丝数量的减少导致存储器芯片空间节省空间，并且由于更少的熔丝被熔化和读取而节省了功率消耗。 由于熔断器计数减少，存储器芯片的裸片的产量也可能由于缺少熔丝数量不足或保险丝熔断失败而得到改善。 对地址熔丝使用有效的默认状态反转可以进一步减少需要熔断的熔断器的平均数，以修复给定的非冗余存储器地址。 由于管理摘要的规则，本摘要不应用于解释索赔。

公开(公告)号：US11720163B2

公开(公告)日：2023-08-08

申请号：US17870696

申请日：2022-07-21

Applicant: Micron Technology, Inc.

Inventor： Greg Blodgett ,  Daniele Balluchi ,  Danilo Caraccio ,  Graziano Mirichigni

IPC: G06F1/32 ,  G06F11/30 ,  G06F1/3234 ,  G06F13/16 ,  G11C5/14 ,  G06F1/30 ,  G06F1/3212 ,  G11C16/30 ,  G11C11/4072 ,  G11C11/4074 ,  G11C16/20

CPC classification number: G06F1/3275 ,  G06F1/305 ,  G06F1/3212 ,  G06F11/3062 ,  G06F13/1668 ,  G11C5/142 ,  G11C5/144 ,  G11C11/4072 ,  G11C11/4074 ,  G11C16/20 ,  G11C16/30

Abstract: The present disclosure includes apparatuses and methods for providing energy information to memory. An embodiment includes determining, by a host, that a charge level of an energy source coupled to the host has reached or exceeded a threshold value, and transmitting, from the host to a memory device coupled to the host, signaling indicative of an energy mode for the memory device, wherein the signaling is transmitted based at least in part on determining that the charge level of the energy source has reached or exceeded the threshold.

公开(公告)号：US09064587B2

公开(公告)日：2015-06-23

申请号：US13911863

申请日：2013-06-06

Applicant: Micron Technology, Inc.

Inventor： Greg Blodgett

IPC: G11C17/18 ,  G11C17/16 ,  G11C29/00

CPC classification number: G11C17/16 ,  G11C29/787 ,  G11C29/812

Abstract: A memory chip design methodology is disclosed wherein fuse banks on the memory chip may be implemented without enable fuses. A fuse bank may be enabled by using one or more least significant bits (LSBs) in the memory address stored in the fuse bank, thereby avoiding the need for a separate enable fuse. A reduction in the number of fuses results in space savings on the memory chip real estate and also savings in power consumption because of fewer fuses to be blown and read. With reduced fuse count, the yield of the memory chip's die may also be improved because of less number of defective fuses or failed fuse blows. The use of effective default state inversion for address fuses may further reduce the average number of fuses that need to be blown to repair a given non-redundant memory address. Because of the rules governing abstracts, this abstract should not be used to construe the claims.