公开(公告)号：US20150357233A1

公开(公告)日：2015-12-10

申请号：US14828371

申请日：2015-08-17

Applicant: Micron Technology, Inc.

Inventor： H. Montgomery Manning

IPC: H01L21/768 ,  H01L27/108 ,  H01L21/8234

CPC classification number: H01L27/105 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823475 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10814 ,  H01L27/10844 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/1104

Abstract: The present technique relates to a method and apparatus to provide a dielectric etch stop layer that prevents shorts for a buried digit layer as an interconnect. In a memory device, such as DRAM or SRAM, various layers are deposited to form structures, such as PMOS gates, NMOS gates, memory cells, P+ active areas, and N+ active areas. These structures are fabricated through the use of multiple masking processes, which may cause shorts when a buried digit layer is deposited if the masking processes are misaligned. Accordingly, a dielectric etch stop layer, such as aluminum oxide Al2O3 or silicon carbide SiC, may be utilized in the array to prevent shorts between the wordlines, active areas, and the buried digit layer when the contacts are misaligned.

Abstract translation: 本技术涉及一种提供电介质蚀刻停止层的方法和装置，其防止掩埋数字层作为互连的短路。 在诸如DRAM或SRAM的存储器件中，沉积各种层以形成诸如PMOS栅极，NMOS栅极，存储器单元，P +有源区域和N +有源区域之类的结构。 这些结构是通过使用多个掩模过程来制造的，当掩蔽过程不对准时，当掩埋数位层被沉积时，这可能导致短路。 因此，可以在阵列中使用电介质蚀刻停止层，例如氧化铝Al 2 O 3或碳化硅SiC，以防止当触点不对准时字线，有源区和掩埋数字层之间的短路。

公开(公告)号：US20240029794A1

公开(公告)日：2024-01-25

申请号：US17868118

申请日：2022-07-19

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Anna Maria Conti ,  Harsh Narendrakumar Jain ,  H. Montgomery Manning

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11582

Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack extends from a memory-array region into a stair-step region. The first tiers are conductive and the second tiers are insulative at least in a finished-circuitry construction. A first layer of imageable resist is exposed to actinic radiation and developed to form a first opening there-through in the stair-step region. The developed first layer is used in a plurality of alternating etching and lateral-trimming steps that widens the first opening and forms two opposing flights of stairs in the stack in the stair-step region. A second layer of imageable resist is formed directly above the two opposing flights of stairs. The second layer is exposed to actinic radiation and developed to form a second opening there-through. The second opening exposes all of the stairs of one of the two opposing flights. The second layer is directly above all of the stairs in the other of the two opposing flights. The developed second layer is used in a plurality of alternating etching and lateral-trimming steps that widens the second opening, lengthens at least one of the two opposing flights of stairs, and extends the two opposing flights of stairs deeper into the stack. Other embodiments, including structure, are disclosed.