公开(公告)号：US20210013213A1

公开(公告)日：2021-01-14

申请号：US16504681

申请日：2019-07-08

Applicant: Micron Technology, Inc.

Inventor： Dojun Kim ,  Christopher W. Petz ,  Sanket S. Kelkar ,  Hidekazu Nobuto

IPC: H01L27/108 ,  G11C5/06

Abstract: An apparatus comprising a memory array comprising access lines. Each of the access lines comprises an insulating material adjacent a bottom surface and sidewalls of a base material, a first conductive material adjacent the insulating material, a second conductive material adjacent the first conductive material, and a barrier material between the first conductive material and the second conductive material. The barrier material is configured to suppress migration of reactive species from the second conductive material. Methods of forming the apparatus and electronic systems are also disclosed.

公开(公告)号：US20210126103A1

公开(公告)日：2021-04-29

申请号：US16667654

申请日：2019-10-29

Applicant: Micron Technology, Inc.

Inventor： Hidekazu Nobuto

IPC: H01L29/49 ,  H01L27/108 ,  H01L29/423 ,  H01L23/532 ,  H01L29/40 ,  H01L21/28 ,  H01L21/285

Abstract: An apparatus comprising a wordline in a material, the wordline comprising a first metal portion, a second metal portion vertically adjacent to the first metal portion, and a third metal portion vertically adjacent to the second metal portion. A dielectric material is between the wordline and the material. Additional apparatus are disclosed, as are related methods of forming an apparatus and electronic systems.

公开(公告)号：US09768177B2

公开(公告)日：2017-09-19

申请号：US14817458

申请日：2015-08-04

Applicant: Micron Technology, Inc.

Inventor： Hidekazu Nobuto

IPC: H01L21/4763 ,  H01L27/108 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L27/10891 ,  C23C16/045 ,  C23C16/14 ,  C23C16/45525 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/4236

Abstract: A method of forming conductive material of a buried transistor gate line includes adhering a precursor comprising tungsten and chlorine to material within a substrate trench. The precursor is reduced with hydrogen to form elemental-form tungsten material over the material within the substrate trench from the precursor.

公开(公告)号：US11322502B2

公开(公告)日：2022-05-03

申请号：US16504681

申请日：2019-07-08

Applicant: Micron Technology, Inc.

Inventor： Dojun Kim ,  Christopher W. Petz ,  Sanket S. Kelkar ,  Hidekazu Nobuto

IPC: H01L27/108 ,  G11C5/06

Abstract: An apparatus comprising a memory array comprising access lines. Each of the access lines comprises an insulating material adjacent a bottom surface and sidewalls of a base material, a first conductive material adjacent the insulating material, a second conductive material adjacent the first conductive material, and a barrier material between the first conductive material and the second conductive material. The barrier material is configured to suppress migration of reactive species from the second conductive material. Methods of forming the apparatus and electronic systems are also disclosed.

公开(公告)号：US20210296167A1

公开(公告)日：2021-09-23

申请号：US17340410

申请日：2021-06-07

Applicant: Micron Technology, Inc.

Inventor： Kenichi Kusumoto ,  Taizo Yasuda ,  Hidekazu Nobuto ,  Kohei Morita

IPC: H01L21/768 ,  H01L21/28

Abstract: Microelectronic devices—having at least one conductive contact structure adjacent a silicide region—are formed using methods that avoid unintentional contact expansion and contact reduction. A first metal nitride liner is formed in a contact opening, and an exposed surface of a polysilicon structure is thereafter treated (e.g., cleaned and dried) in preparation for formation of a silicide region. During the pretreatments (e.g., cleaning and drying), neighboring dielectric material is protected by the presence of the metal nitride liner, inhibiting expansion of the contact opening. After forming the silicide region, a second metal nitride liner is formed on the silicide region before a conductive material is formed to fill the contact opening and form a conductive contact structure (e.g., a memory cell contact structure, a peripheral contact structure).

公开(公告)号：US10002874B2

公开(公告)日：2018-06-19

申请号：US15641071

申请日：2017-07-03

Applicant: Micron Technology, Inc.

Inventor： Hidekazu Nobuto

IPC: H01L21/4763 ,  H01L27/108 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L27/10891 ,  C23C16/045 ,  C23C16/14 ,  C23C16/45525 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/4236

Abstract: A method of forming conductive material of a buried transistor gate line includes adhering a precursor comprising tungsten and chlorine to material within a substrate trench. The precursor is reduced with hydrogen to form elemental-form tungsten material over the material within the substrate trench from the precursor.

公开(公告)号：US20170317086A1

公开(公告)日：2017-11-02

申请号：US15641071

申请日：2017-07-03

Applicant: Micron Technology, Inc.

Inventor： Hidekazu Nobuto

IPC: H01L27/108 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L27/10891 ,  C23C16/045 ,  C23C16/14 ,  C23C16/45525 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/4236

Abstract: A method of forming conductive material of a buried transistor gate line includes adhering a precursor comprising tungsten and chlorine to material within a substrate trench. The precursor is reduced with hydrogen to form elemental-form tungsten material over the material within the substrate trench from the precursor.

公开(公告)号：US11043414B2

公开(公告)日：2021-06-22

申请号：US16654865

申请日：2019-10-16

Applicant: Micron Technology, Inc.

Inventor： Kenichi Kusumoto ,  Taizo Yasuda ,  Hidekazu Nobuto ,  Kohei Morita

IPC: H01L21/768 ,  H01L21/28 ,  H01L29/49 ,  H01L21/285

Abstract: Microelectronic devices—having at least one conductive contact structure adjacent a silicide region—are formed using methods that avoid unintentional contact expansion and contact reduction. A first metal nitride liner is formed in a contact opening, and an exposed surface of a polysilicon structure is thereafter treated (e.g., cleaned and dried) in preparation for formation of a silicide region. During the pretreatments (e.g., cleaning and drying), neighboring dielectric material is protected by the presence of the metal nitride liner, inhibiting expansion of the contact opening. After forming the silicide region, a second metal nitride liner is formed on the silicide region before a conductive material is formed to fill the contact opening and form a conductive contact structure (e.g., a memory cell contact structure, a peripheral contact structure).

公开(公告)号：US20210118676A1

公开(公告)日：2021-04-22

申请号：US16654865

申请日：2019-10-16

Applicant: Micron Technology, Inc.

Inventor： Kenichi Kusumoto ,  Taizo Yasuda ,  Hidekazu Nobuto ,  Kohei Morita

IPC: H01L21/02 ,  H01L21/203

Abstract: Microelectronic devices—having at least one conductive contact structure adjacent a silicide region—are formed using methods that avoid unintentional contact expansion and contact reduction. A first metal nitride liner is formed in a contact opening, and an exposed surface of a polysilicon structure is thereafter treated (e.g., cleaned and dried) in preparation for formation of a silicide region. During the pretreatments (e.g., cleaning and drying), neighboring dielectric material is protected by the presence of the metal nitride liner, inhibiting expansion of the contact opening. After forming the silicide region, a second metal nitride liner is formed on the silicide region before a conductive material is formed to fill the contact opening and form a conductive contact structure (e.g., a memory cell contact structure, a peripheral contact structure).