公开(公告)号：US20230118874A1

公开(公告)日：2023-04-20

申请号：US16976286

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Jingwei Cheng ,  Cheng Zhang

IPC: G06F3/06

Abstract: Methods, systems, and devices for configurable memory die capacitance are described. A memory device may include a capacitive component, which may include one or more capacitors and associated switching components. The capacitive component may be coupled with an input/output (I/O) pad and an associated input buffer, and the one or more capacitors of the capacitive component may be selectively couplable with the I/O pad via the switching components. Switching components may be activated individually, in coordination, or not at all, such that one, multiple, or none of the capacitors may be coupled with the I/O pad. The capacitive component, I/O pad, and input buffer may be included in a same die of the memory device. In some cases, a configuration of the capacitive component may be based on signaling received from a host device.

公开(公告)号：US20250118385A1

公开(公告)日：2025-04-10

申请号：US18923244

申请日：2024-10-22

Applicant: Micron Technology, Inc.

Inventor： Chunqiang Weng ,  Jingwei Cheng

IPC: G11C29/56

Abstract: Methods, systems, and devices for testing circuit for a memory device are described. An apparatus may include a memory system including contacts that route signals to different regions of the memory system. The apparatus may include a first substrate including a memory system interface coupled with the memory system and a probe interface. The apparatus may also include a second substrate coupled with a host system interface of the first substrate and receive the signal of the memory system from the memory system interface. The first interface may route a signal of the memory system to the probe interface and a tester to determine the signal's integrity and any errors associated with the memory system. The first substrate may include a resistor coupled with the contacts of the memory system, the resistor on a surface of the interface may be configured to improve the signal at the tester.

公开(公告)号：US12142332B2

公开(公告)日：2024-11-12

申请号：US17939491

申请日：2022-09-07

Applicant: Micron Technology, Inc.

Inventor： Chunqiang Weng ,  Jingwei Cheng

IPC: G11C29/12

Abstract: Methods, systems, and devices for testing circuit for a memory device are described. An apparatus may include a memory system including contacts that route signals to different regions of the memory system. The apparatus may include a first substrate including a memory system interface coupled with the memory system and a probe interface. The apparatus may also include a second substrate coupled with a host system interface of the first substrate and receive the signal of the memory system from the memory system interface. The first interface may route a signal of the memory system to the probe interface and a tester to determine the signal's integrity and any errors associated with the memory system. The first substrate may include a resistor coupled with the contacts of the memory system, the resistor on a surface of the interface may be configured to improve the signal at the tester.

公开(公告)号：US20230077784A1

公开(公告)日：2023-03-16

申请号：US17939491

申请日：2022-09-07

Applicant: Micron Technology, Inc.

Inventor： Chunqiang Weng ,  Jingwei Cheng

IPC: G11C29/12

Abstract: Methods, systems, and devices for testing circuit for a memory device are described. An apparatus may include a memory system including contacts that route signals to different regions of the memory system. The apparatus may include a first substrate including a memory system interface coupled with the memory system and a probe interface. The apparatus may also include a second substrate coupled with a host system interface of the first substrate and receive the signal of the memory system from the memory system interface. The first interface may route a signal of the memory system to the probe interface and a tester to determine the signal's integrity and any errors associated with the memory system. The first substrate may include a resistor coupled with the contacts of the memory system, the resistor on a surface of the interface may be configured to improve the signal at the tester.

公开(公告)号：US20240295975A1

公开(公告)日：2024-09-05

申请号：US18604203

申请日：2024-03-13

Applicant: Micron Technology, Inc.

Inventor： Jingwei Cheng ,  Cheng Zhang

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/10

CPC classification number: G06F3/0629 ,  G06F3/0679 ,  G06F13/1668 ,  G11C7/10

Abstract: Methods, systems, and devices for configurable memory die capacitance are described. A memory device may include a capacitive component, which may include one or more capacitors and associated switching components. The capacitive component may be coupled with an input/output (I/O) pad and an associated input buffer, and the one or more capacitors of the capacitive component may be selectively couplable with the I/O pad via the switching components. Switching components may be activated individually, in coordination, or not at all, such that one, multiple, or none of the capacitors may be coupled with the I/O pad. The capacitive component, I/O pad, and input buffer may be included in a same die of the memory device. In some cases, a configuration of the capacitive component may be based on signaling received from a host device.

公开(公告)号：US11947813B2

公开(公告)日：2024-04-02

申请号：US16976286

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Jingwei Cheng ,  Cheng Zhang

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/10

CPC classification number: G06F3/0629 ,  G06F3/0679 ,  G06F13/1668 ,  G11C7/10

Abstract: Methods, systems, and devices for configurable memory die capacitance are described. A memory device may include a capacitive component, which may include one or more capacitors and associated switching components. The capacitive component may be coupled with an input/output (I/O) pad and an associated input buffer, and the one or more capacitors of the capacitive component may be selectively couplable with the I/O pad via the switching components. Switching components may be activated individually, in coordination, or not at all, such that one, multiple, or none of the capacitors may be coupled with the I/O pad. The capacitive component, I/O pad, and input buffer may be included in a same die of the memory device. In some cases, a configuration of the capacitive component may be based on signaling received from a host device.

公开(公告)号：US11923023B2

公开(公告)日：2024-03-05

申请号：US16982912

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Jingwei Cheng

IPC: G11C16/04 ,  G11C29/12 ,  G11C29/44

CPC classification number: G11C29/1201 ,  G11C29/12015 ,  G11C29/44

Abstract: Methods, systems, and devices for debug capabilities of a memory system with a pin are described. An apparatus may include a memory system that includes a plurality of pins of a first type that are configured to communicate information as part of operating the memory system and a pin of a second type. The apparatus may also include a circuit coupled with the memory system, the circuit including a resistor that is coupled with the pin of the second type. The memory system may include a controller that selects a value for the resistor and generates a code as part of a memory management operation to determine one or more operating conditions of the memory system based on selecting the value. The memory system controller may also determine an error associated with the code based on generating the code and the selected value of the resistor.

公开(公告)号：US20230207035A1

公开(公告)日：2023-06-29

申请号：US16982912

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Jingwei Cheng

IPC: G11C29/12 ,  G11C29/44

CPC classification number: G11C29/1201 ,  G11C29/12015 ,  G11C29/44

Abstract: Methods, systems, and devices for debug capabilities of a memory system with a pin are described. An apparatus may include a memory system that includes a plurality of pins of a first type that are configured to communicate information as part of operating the memory system and a pin of a second type. The apparatus may also include a circuit coupled with the memory system, the circuit including a resistor that is coupled with the pin of the second type. The memory system may include a controller that selects a value for the resistor and generates a code as part of a memory management operation to determine one or more operating conditions of the memory system based on selecting the value. The memory system controller may also determine an error associated with the code based on generating the code and the selected value of the resistor.