公开(公告)号：US11322388B2

公开(公告)日：2022-05-03

申请号：US16549594

申请日：2019-08-23

Applicant: Micron Technology, Inc.

Inventor： Vivek Yadav ,  Shen Hu ,  Kangle Li ,  Sanjeev Sapra

IPC: H01L21/762 ,  H01L27/108 ,  H01L21/67 ,  H01L21/02

Abstract: An example method includes patterning a working surface of a semiconductor wafer. The example method includes performing a first deposition of a dielectric material in high aspect ratio trenches. The example method further includes performing a high pressure, high temperature vapor etch to recess the dielectric material in the trenches and performing a second deposition of the dielectric material to continue filling the trenches.

公开(公告)号：US20220285357A1

公开(公告)日：2022-09-08

申请号：US17194859

申请日：2021-03-08

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang ,  Vinay Nair ,  Devesh Dadhich Shreeram ,  Ashwin Panday ,  Kangle Li ,  Zhiqiang Xie ,  Silvia Borsari ,  Mohd Kamran Akhtar ,  Si-Woo Lee

IPC: H01L27/108

Abstract: Some embodiments include an integrated assembly having digit-line-contact-regions between pairs of capacitor-contact-regions. The capacitor-contact-regions are arranged with six adjacent capacitor-contact-regions in a substantially rectangular configuration. Conductive plugs are coupled with the capacitor-contact-regions. Conductive redistribution material is coupled with the conductive plugs. Upper surfaces of the conductive redistribution material are arranged in a substantially hexagonal-close-packed configuration. Digit lines are over the digit-line-contact-regions. Insulative regions are between the digit lines and the conductive plugs. The insulative regions contain voids and/or low-k dielectric material. Capacitors are coupled with the upper surfaces of the conductive redistribution material.

公开(公告)号：US20240088211A1

公开(公告)日：2024-03-14

申请号：US17944649

申请日：2022-09-14

Applicant: Micron Technology, Inc.

Inventor： Devesh Dadhich Shreeram ,  Sanjeev Sapra ,  Kangle Li ,  Sevim Korkmaz

IPC: H01L49/02

CPC classification number: H01L28/92 ,  H01L27/108

Abstract: Methods, apparatuses, and systems related to an over-sculpted storage node are described. An example method includes forming an opening in a pattern of materials. The method further includes performing an etch to over-sculpt the opening. The method further includes depositing a storage node material in the over-sculpted opening to form an over-sculpted storage node. The method further includes performing an etch to remove portions of the pattern of materials. The method further includes performing an etch on the storage node material to trim the over-sculpted storage node.

公开(公告)号：US11563008B2

公开(公告)日：2023-01-24

申请号：US17194859

申请日：2021-03-08

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang ,  Vinay Nair ,  Devesh Dadhich Shreeram ,  Ashwin Panday ,  Kangle Li ,  Zhiqiang Xie ,  Silvia Borsari ,  Mohd Kamran Akhtar ,  Si-Woo Lee

IPC: H01L27/108

Abstract: Some embodiments include an integrated assembly having digit-line-contact-regions between pairs of capacitor-contact-regions. The capacitor-contact-regions are arranged with six adjacent capacitor-contact-regions in a substantially rectangular configuration. Conductive plugs are coupled with the capacitor-contact-regions. Conductive redistribution material is coupled with the conductive plugs. Upper surfaces of the conductive redistribution material are arranged in a substantially hexagonal-close-packed configuration. Digit lines are over the digit-line-contact-regions. Insulative regions are between the digit lines and the conductive plugs. The insulative regions contain voids and/or low-k dielectric material. Capacitors are coupled with the upper surfaces of the conductive redistribution material.

公开(公告)号：US20220238532A1

公开(公告)日：2022-07-28

申请号：US17647902

申请日：2022-01-13

Applicant: Micron Technology, Inc.

Inventor： Devesh Dadhich Shreeram ,  Kangle Li ,  Matthew N. Rocklein ,  Wei Ching Huang ,  Ping-Cheng Hsu ,  Sevim Korkmaz ,  Sanjeev Sapra ,  An-Jen B. Cheng

IPC: H01L27/108

Abstract: A DRAM capacitor may include a first capacitor electrode, a capacitor dielectric adjacent to the first capacitor electrode, and a second capacitor electrode adjacent to the capacitor dielectric. The first capacitor electrode may include a lower portion, an upper portion, and a step transition between the lower portion and the upper portion, a width of the upper portion of the first capacitor electrode at the step transition is less than a width of the lower portion of the first capacitor electrode at the step transition. Semiconductor devices, systems, and methods are also disclosed.

公开(公告)号：US12193208B2

公开(公告)日：2025-01-07

申请号：US17647902

申请日：2022-01-13

Applicant: Micron Technology, Inc.

Inventor： Devesh Dadhich Shreeram ,  Kangle Li ,  Matthew N. Rocklein ,  Wei Ching Huang ,  Ping-Cheng Hsu ,  Sevim Korkmaz ,  Sanjeev Sapra ,  An-Jen B. Cheng

IPC: H10B12/00

Abstract: A DRAM capacitor may include a first capacitor electrode, a capacitor dielectric adjacent to the first capacitor electrode, and a second capacitor electrode adjacent to the capacitor dielectric. The first capacitor electrode may include a lower portion, an upper portion, and a step transition between the lower portion and the upper portion, a width of the upper portion of the first capacitor electrode at the step transition is less than a width of the lower portion of the first capacitor electrode at the step transition. Semiconductor devices, systems, and methods are also disclosed.

公开(公告)号：US11114443B2

公开(公告)日：2021-09-07

申请号：US16555565

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Vivek Yadav ,  Fatma Arzum Simsek-Ege ,  Sanjeev Sapra ,  Thomas A. Figura ,  Kangle Li

IPC: H01L27/108 ,  H01L29/78 ,  H01L21/67 ,  H01L21/762

Abstract: Systems, apparatuses, and methods related to semiconductor structure formation are described. An example method may include patterning a working surface of a semiconductor wafer. The method may further include performing a vapor etch on a first dielectric material at the working surface to recess the first dielectric material to a first intended depth of an opening relative to the working surface and to expose a second dielectric material on a sidewall of the opening. The method may further include performing a wet etch on the second dielectric material to recess the second dielectric material to the intended depth.

公开(公告)号：US20210066307A1

公开(公告)日：2021-03-04

申请号：US16555565

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Vivek Yadav ,  Fatma Arzum Simsek-Ege ,  Sanjeev Sapra ,  Thomas A. Figura ,  Kangle Li

IPC: H01L27/108

Abstract: Systems, apparatuses, and methods related to semiconductor structure formation are described. An example method may include patterning a working surface of a semiconductor wafer. The method may further include performing a vapor etch on a first dielectric material at the working surface to recess the first dielectric material to a first intended depth of an opening relative to the working surface and to expose a second dielectric material on a sidewall of the opening. The method may further include performing a wet etch on the second dielectric material to recess the second dielectric material to the intended depth.

公开(公告)号：US20210057266A1

公开(公告)日：2021-02-25

申请号：US16549594

申请日：2019-08-23

Applicant: Micron Technology, Inc.

Inventor： Vivek Yadav ,  Shen Hu ,  Kangle Li ,  Sanjeev Sapra

IPC: H01L21/762 ,  H01L27/108 ,  H01L21/02 ,  H01L21/67

Abstract: An example method includes patterning a working surface of a semiconductor wafer. The example method includes performing a first deposition of a dielectric material in high aspect ratio trenches. The example method further includes performing a high pressure, high temperature vapor etch to recess the dielectric material in the trenches and performing a second deposition of the dielectric material to continue filling the trenches.