公开(公告)号：US11127588B2

公开(公告)日：2021-09-21

申请号：US16383159

申请日：2019-04-12

Applicant: Micron Technology, Inc.

Inventor： Sevim Korkmaz ,  Sanjeev Sapra ,  Jerome A. Imonigie ,  Armin Saeedi Vahdat

IPC: H01L21/02 ,  H01L27/108 ,  H01L49/02 ,  H01L21/67

Abstract: Methods, apparatuses, and systems related to semiconductor processing (e.g., of a capacitor support structure) are described. An example method includes patterning a surface of a semiconductor substrate to have a first silicate material, a nitride material over the first silicate material, and a second silicate material over the nitride material. The method further includes removing the first silicate material and the second silicate material and leaving the nitride material as a support structure for a column formed from a capacitor material. The method further includes performing supercritical drying on the column, after removal of the first and second silicate materials, to reduce a probability of the column wobbling relative to otherwise drying the column after the removal of the first and second silicate materials.

公开(公告)号：US10985239B2

公开(公告)日：2021-04-20

申请号：US16543065

申请日：2019-08-16

Applicant: Micron Technology, Inc.

Inventor： Matthew N. Rocklein ,  An-Jen B. Cheng ,  Fredrick D. Fishburn ,  Sevim Korkmaz ,  Paul A. Paduano

IPC: H01L49/02 ,  H01L21/285 ,  H01L21/311 ,  H01L21/02

Abstract: Methods, apparatuses, and systems related to trim a semiconductor structure using oxygen are described. An example method includes forming a support structure for a semiconductor structure having a first silicate material on a working surface. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes forming an opening through the semiconductor structure. The method further includes depositing an electrode material within the opening. The method further includes removing portions of the support structure. The method further includes performing a controlled oxidative trim to an upper portion of the electrode material.

公开(公告)号：US20200381437A1

公开(公告)日：2020-12-03

申请号：US16423684

申请日：2019-05-28

Applicant: Micron Technology, Inc.

Inventor： Sevim Korkmaz ,  Devesh Dadhich Shreeram ,  Srinivasan Balakrishnan ,  Dewali Ray ,  Sanjeev Sapra ,  Paul A. Paduano

IPC: H01L27/108 ,  H01L49/02

Abstract: Methods, apparatuses, and systems related to removing a hard mask are described. An example method includes patterning a silicon hard mask on a semiconductor structure having a first silicate material on a working surface. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes an opening through the semiconductor structure using the patterned hard mask to form a pillar support. The method further includes forming a silicon liner material on the semiconductor structure. The method further includes removing the silicon liner material using a wet etch process.

公开(公告)号：US12193208B2

公开(公告)日：2025-01-07

申请号：US17647902

申请日：2022-01-13

Applicant: Micron Technology, Inc.

Inventor： Devesh Dadhich Shreeram ,  Kangle Li ,  Matthew N. Rocklein ,  Wei Ching Huang ,  Ping-Cheng Hsu ,  Sevim Korkmaz ,  Sanjeev Sapra ,  An-Jen B. Cheng

IPC: H10B12/00

Abstract: A DRAM capacitor may include a first capacitor electrode, a capacitor dielectric adjacent to the first capacitor electrode, and a second capacitor electrode adjacent to the capacitor dielectric. The first capacitor electrode may include a lower portion, an upper portion, and a step transition between the lower portion and the upper portion, a width of the upper portion of the first capacitor electrode at the step transition is less than a width of the lower portion of the first capacitor electrode at the step transition. Semiconductor devices, systems, and methods are also disclosed.

公开(公告)号：US20200243258A1

公开(公告)日：2020-07-30

申请号：US16258904

申请日：2019-01-28

Applicant: Micron Technology, Inc.

Inventor： Devesh Dadhich Shreeram ,  Sevim Korkmaz ,  Jian Li ,  Sanjeev Sapra ,  Dewali Ray

IPC: H01G4/008 ,  H01G4/08 ,  H01L49/02

Abstract: Methods, apparatuses, and systems related to forming a capacitor using a sacrificial material are described. An example method includes forming a first silicate material on a substrate. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes forming a sacrificial material on the second nitride material. The method further includes forming a column of capacitor material through the first silicate material, the first nitride material, the second silicate material, the second nitride material, and the sacrificial material. The method further includes removing the sacrificial material to expose a top portion of the capacitor material.

公开(公告)号：US20240088211A1

公开(公告)日：2024-03-14

申请号：US17944649

申请日：2022-09-14

Applicant: Micron Technology, Inc.

Inventor： Devesh Dadhich Shreeram ,  Sanjeev Sapra ,  Kangle Li ,  Sevim Korkmaz

IPC: H01L49/02

CPC classification number: H01L28/92 ,  H01L27/108

Abstract: Methods, apparatuses, and systems related to an over-sculpted storage node are described. An example method includes forming an opening in a pattern of materials. The method further includes performing an etch to over-sculpt the opening. The method further includes depositing a storage node material in the over-sculpted opening to form an over-sculpted storage node. The method further includes performing an etch to remove portions of the pattern of materials. The method further includes performing an etch on the storage node material to trim the over-sculpted storage node.

公开(公告)号：US20220238532A1

公开(公告)日：2022-07-28

申请号：US17647902

申请日：2022-01-13

Applicant: Micron Technology, Inc.

Inventor： Devesh Dadhich Shreeram ,  Kangle Li ,  Matthew N. Rocklein ,  Wei Ching Huang ,  Ping-Cheng Hsu ,  Sevim Korkmaz ,  Sanjeev Sapra ,  An-Jen B. Cheng

IPC: H01L27/108

Abstract: A DRAM capacitor may include a first capacitor electrode, a capacitor dielectric adjacent to the first capacitor electrode, and a second capacitor electrode adjacent to the capacitor dielectric. The first capacitor electrode may include a lower portion, an upper portion, and a step transition between the lower portion and the upper portion, a width of the upper portion of the first capacitor electrode at the step transition is less than a width of the lower portion of the first capacitor electrode at the step transition. Semiconductor devices, systems, and methods are also disclosed.

公开(公告)号：US11011521B2

公开(公告)日：2021-05-18

申请号：US16423684

申请日：2019-05-28

Applicant: Micron Technology, Inc.

Inventor： Sevim Korkmaz ,  Devesh Dadhich Shreeram ,  Srinivasan Balakrishnan ,  Dewali Ray ,  Sanjeev Sapra ,  Paul A. Paduano

IPC: H01L27/108 ,  H01L49/02

Abstract: Methods, apparatuses, and systems related to removing a hard mask are described. An example method includes patterning a silicon hard mask on a semiconductor structure having a first silicate material on a working surface. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes an opening through the semiconductor structure using the patterned hard mask to form a pillar support. The method further includes forming a silicon liner material on the semiconductor structure. The method further includes removing the silicon liner material using a wet etch process.

公开(公告)号：US10964475B2

公开(公告)日：2021-03-30

申请号：US16258904

申请日：2019-01-28

Applicant: Micron Technology, Inc.

Inventor： Devesh Dadhich Shreeram ,  Sevim Korkmaz ,  Jian Li ,  Sanjeev Sapra ,  Dewali Ray

IPC: H01L49/02 ,  H01G4/008 ,  H01G4/08

Abstract: Methods, apparatuses, and systems related to forming a capacitor using a sacrificial material are described. An example method includes forming a first silicate material on a substrate. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes forming a sacrificial material on the second nitride material. The method further includes forming a column of capacitor material through the first silicate material, the first nitride material, the second silicate material, the second nitride material, and the sacrificial material. The method further includes removing the sacrificial material to expose a top portion of the capacitor material.

公开(公告)号：US20210050409A1

公开(公告)日：2021-02-18

申请号：US16543065

申请日：2019-08-16

Applicant: Micron Technology, Inc.

Inventor： Matthew N. Rocklein ,  An-Jen B. Cheng ,  Fredrick D. Fishburn ,  Sevim Korkmaz ,  Paul A. Paduano

IPC: H01L49/02 ,  H01L21/285 ,  H01L21/02 ,  H01L21/311

Abstract: Methods, apparatuses, and systems related to trim a semiconductor structure using oxygen are described. An example method includes forming a support structure for a semiconductor structure having a first silicate material on a working surface. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes forming an opening through the semiconductor structure. The method further includes depositing an electrode material within the opening. The method further includes removing portions of the support structure. The method further includes performing a controlled oxidative trim to an upper portion of the electrode material.