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公开(公告)号：US11996144B2
公开(公告)日：2024-05-28
申请号：US17840779
申请日：2022-06-15
发明人： Jon D. Trantham , Praveen Viraraghavan , John W. Dykes , Ian J. Gilbert , Sangita Shreedharan Kalarickal , Matthew J. Totin , Mohamad El-Batal , Darshana H. Mehta
CPC分类号： G11C11/5657 , G11C11/221 , G11C11/223 , G11C11/2273 , G11C11/2275
摘要： A non-volatile memory (NVM) is formed of memory cells each having multiple ferroelectric memory elements (FMEs). Each FME stores data in relation to an electrical polarity of a recording layer formed of ferroelectric or anti-ferroelectric material. Each multi-FME memory cell is coupled to a set of external control lines activated by a control circuit in a selected order to perform program and/or read operations upon the FMEs. The FMEs may share a nominally identical construction or may have different constructions. Data are programmed and written responsive to the respective program/read responses of the FMEs. Constructions can include ferroelectric tunneling junctions (FTJs), ferroelectric random access memory (FeRAM), and ferroelectric field effect transistors (FeFETs). The NVM may form a portion of a data storage device, such as a solid-state drive (SSD).
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公开(公告)号：US11990166B2
公开(公告)日：2024-05-21
申请号：US18316641
申请日：2023-05-12
申请人： Resonac Corporation
发明人： Masaaki Yanagisawa
CPC分类号： G11B9/02 , G11C11/22 , G11C11/221 , G11C11/5657 , G11B5/21
摘要： A ferroelectric recording medium includes an electrode layer, a ferroelectric recording layer, and a protection layer formed in this order on a substrate, wherein the ferroelectric recording layer includes a ferroelectric layer, the ferroelectric layer has an amorphous structure with short-range order, a distance of the short-range order is equal to or less than 2 nm, and a lattice constant of the amorphous structure and the lattice constant of the material constituting the substrate are lattice-matched within a range of ±10%.
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公开(公告)号：US20240071453A1
公开(公告)日：2024-02-29
申请号：US18447997
申请日：2023-08-10
发明人： Perng-Fei Yuh
CPC分类号： G11C11/223 , G11C11/2259 , G11C11/2273 , G11C11/2275 , G11C11/5657 , H10B51/00
摘要： A memory device includes a plurality of memory cells. Each memory cell includes a multi-gate FeFET that has a first source/drain terminal, a second source/drain terminal, and a gate with a plurality of ferroelectric layers configured such that each of the ferroelectric layers has a respective unique switching E-field.
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公开(公告)号：US11881242B2
公开(公告)日：2024-01-23
申请号：US17816143
申请日：2022-07-29
发明人： Perng-Fei Yuh
CPC分类号： G11C11/223 , G11C11/2259 , G11C11/2273 , G11C11/2275 , G11C11/5657 , H10B51/00
摘要： A memory device includes a plurality of memory cells. Each memory cell includes a multi-gate FeFET that has a first source/drain terminal, a second source/drain terminal, and a gate with a plurality of ferroelectric layers configured such that each of the ferroelectric layers has a respective unique switching E-field.
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公开(公告)号：US20190189178A1
公开(公告)日：2019-06-20
申请号：US15846765
申请日：2017-12-19
发明人： Daniele Vimercati
CPC分类号： G11C11/2273 , G11C11/221 , G11C11/2275 , G11C11/2293 , G11C11/2297 , G11C11/5657 , G11C13/004
摘要： The present disclosure includes apparatuses, methods, and systems for current separation for memory sensing. An embodiment includes applying a sensing voltage to a memory cell having a ferroelectric material, and determining a data state of the memory cell by separating a first current output by the memory cell while the sensing voltage is being applied to the memory cell and a second current output by the memory cell while the sensing voltage is being applied to the memory cell, wherein the first current output by the memory cell corresponds to a first polarization state of the ferroelectric material of the memory cell and the second current output by the memory cell corresponds a second polarization state of the ferroelectric material of the memory cell.
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公开(公告)号：US20190172539A1
公开(公告)日：2019-06-06
申请号：US15829076
申请日：2017-12-01
申请人： NaMLab gGmbH
IPC分类号： G11C14/00 , G11C13/00 , H01L21/28 , H01L27/10 , H01L27/11507
CPC分类号： G11C14/0072 , G11C7/1006 , G11C11/223 , G11C11/2259 , G11C11/5657 , G11C13/0004 , G11C14/009 , H01L27/101 , H01L27/11507 , H01L29/40111 , H03K19/0944
摘要： A polarization-based logic gate includes a transistor having a drain and a polarizable material layer having at least two polarization states, the polarization state representing a first logic value, and a resistive element having a first terminal coupled to the drain and a second terminal. A plurality of input/output terminals connected to the transistor and second terminal of the resistive element so as to apply voltages to selected input/output terminals, including a sensing voltage representing a second logic value, with a resulting drain current of the transistor at least partially flowing through the resistive element and representing a result of a logic operation between the first logic value and the second logic value.
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公开(公告)号：US20190108866A1
公开(公告)日：2019-04-11
申请号：US16188855
申请日：2018-11-13
发明人： Eric S. Carman
CPC分类号： G11C11/225 , G11C8/08 , G11C11/22 , G11C11/221 , G11C11/2253 , G11C11/2273 , G11C11/2275 , G11C11/2293 , G11C11/5657 , G11C13/047
摘要： Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be used to charge a second ferroelectric memory cell by transferring charge from a plate of first ferroelectric memory cell to a plate of the second ferroelectric memory cell. In some examples, prior to the transfer of charge, the first ferroelectric memory cell may be selected for a first operation in which the first ferroelectric memory cell transitions from a charged state to a discharged state and the second ferroelectric memory cell may be selected for a second operation during which the second ferroelectric memory cell transitions from a discharged state to a charged state. The discharging of the first ferroelectric memory cell may be used to assist in charging the second ferroelectric memory cell.
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8.发明申请公开(公告)号：US20190103151A1
公开(公告)日：2019-04-04
申请号：US16194820
申请日：2018-11-19
IPC分类号： G11C11/22 , H01L27/11507 , H01L49/02 , G11C13/04 , H01L27/11502 , G11C14/00 , G11C11/56
CPC分类号： G11C11/225 , G11C11/22 , G11C11/221 , G11C11/2273 , G11C11/2275 , G11C11/2297 , G11C11/5657 , G11C13/047 , G11C14/00 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/56 , H01L28/65 , H01L28/75
摘要： Methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell comprising a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. The method further comprises applying another of the positive bias voltage and the negative bias voltage to the ferroelectric memory cell to switch a polarization of the ferroelectric memory cell, wherein an absolute value of the negative bias voltage is different from an absolute value of the positive bias voltage. Ferroelectric memory cells are also described.
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公开(公告)号：US20190096463A1
公开(公告)日：2019-03-28
申请号：US15859583
申请日：2017-12-31
发明人： Jin Ping Han , Xiao Sun , Teng Yang
IPC分类号： G11C11/22 , H03K19/177
CPC分类号： G11C11/223 , G11C11/2255 , G11C11/2257 , G11C11/2259 , G11C11/2275 , G11C11/54 , G11C11/5621 , G11C11/5628 , G11C11/5657 , G11C11/5671 , G11C16/04 , G11C16/08 , G11C16/10 , H03K19/1776
摘要： Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.
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公开(公告)号：US20180137908A1
公开(公告)日：2018-05-17
申请号：US15858831
申请日：2017-12-29
CPC分类号： G11C11/2275 , G11C11/22 , G11C11/221 , G11C11/2253 , G11C11/2273 , G11C11/5657 , G11C14/00 , H01L27/11502 , H01L27/11507
摘要： Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a non-volatile memory array. Multiple memory cells may be in electronic communication with a common conductive line, and each memory cell may have an electrically non-linear selection component. Following an access operation (e.g., a read or write operation) of a target memory cell, untargeted memory cells may be discharged by applying a discharge voltage to the common conductive line. The discharge voltage may, for example, have a polarity opposite to the access voltage. In other examples, a delay may be instituted between access attempts in order to discharge the untargeted memory cells.
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