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公开(公告)号：US20240130143A1
公开(公告)日：2024-04-18
申请号：US17968744
申请日：2022-10-18
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Agostino Pirovano , Matteo Impalà , Mattia Robustelli , Fabio Pellizzer
CPC classification number: H01L27/2481 , H01L45/06 , H01L45/143 , H01L45/1683
Abstract: A single memory chip including both memory and storage capabilities on the single chip and accompanying process for forming a memory array including both capabilities is disclosed. In particular, the single chip may incorporate the use of two different chalcogenide materials deposited thereon to implement the memory and storage capabilities. Chalcogenide materials provide flexibility on cell performance, such as by changing the chalcogenide material composition. For the single memory chip, one type of chalcogenide material may be utilized to create memory cells and another type of chalcogenide material may be utilized to create storage cells. The process for forming the memory array includes forming first and second openings in a starting structure and performing a series of etching and deposition steps on the structure to form the memory and storage cells using the two different chalcogenide compositions. The memory and storage cells are independently addressable via wordline and bitline selection.
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公开(公告)号：US20250024761A1
公开(公告)日：2025-01-16
申请号：US18782436
申请日：2024-07-24
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Matteo Impalà , Cécile Colette Solange Nail
Abstract: Methods, systems, and devices for random number generation based on threshold voltage randomness are described. For example, a memory device may apply a voltage to a chalcogenide element and increase the applied voltage at least until the applied voltage satisfies a threshold voltage associated with the chalcogenide element. The memory device may detect the state of an oscillating signal at a time at which the applied voltage satisfies the threshold voltage, and the memory device may output a logic value corresponding to the state of the oscillating signal. The threshold voltage of the chalcogenide element may vary in a statistically random manner across voltage applications, and hence the state of the oscillating signal at the time an applied voltage reaches the threshold voltage may likewise vary in a statistically random manner, and thus the corresponding logic value that is output may be a random value suitable for random number generation.
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Patent Agency Ranking
公开(公告)号：US20240057489A1
公开(公告)日：2024-02-15
申请号：US17818617
申请日：2022-08-09
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Matteo Impalà , Cécile Colette Solange Nail
CPC classification number: H01L45/141 , G11C13/003 , H01L45/1233
Abstract: Methods, systems, and devices for random number generation based on threshold voltage randomness are described. For example, a memory device may apply a voltage to a chalcogenide element and increase the applied voltage at least until the applied voltage satisfies a threshold voltage associated with the chalcogenide element. The memory device may detect the state of an oscillating signal at a time at which the applied voltage satisfies the threshold voltage, and the memory device may output a logic value corresponding to the state of the oscillating signal. The threshold voltage of the chalcogenide element may vary in a statistically random manner across voltage applications, and hence the state of the oscillating signal at the time an applied voltage reaches the threshold voltage may likewise vary in a statistically random manner, and thus the corresponding logic value that is output may be a random value suitable for random number generation.
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公开(公告)号：US20240404590A1
公开(公告)日：2024-12-05
申请号：US18742753
申请日：2024-06-13
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Alessandro Sebastiani , Mattia Robustelli , Matteo Impalà
Abstract: Methods, systems, and devices for improved techniques for multi-level memory cell programming are described. A memory array may receive a first command to store a first logic state in a memory cell for storing three or more logic states. The memory array may apply, as part of an erase operation, a first pulse with a first polarity to a plurality of memory cells to store a second logic state different from the first logic state in the plurality of memory cells, where the plurality of memory cells includes the memory cell. The memory array may apply, as part of a write operation or as part of the erase operation, one or more second pulses with a second polarity to the memory cell to store the first logic state in the memory cell based on applying the first pulse.
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公开(公告)号：US12075714B2
公开(公告)日：2024-08-27
申请号：US17818617
申请日：2022-08-09
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Matteo Impalà , Cécile Colette Solange Nail
CPC classification number: H10N70/882 , G11C13/003 , H10N70/826
Abstract: Methods, systems, and devices for random number generation based on threshold voltage randomness are described. For example, a memory device may apply a voltage to a chalcogenide element and increase the applied voltage at least until the applied voltage satisfies a threshold voltage associated with the chalcogenide element. The memory device may detect the state of an oscillating signal at a time at which the applied voltage satisfies the threshold voltage, and the memory device may output a logic value corresponding to the state of the oscillating signal. The threshold voltage of the chalcogenide element may vary in a statistically random manner across voltage applications, and hence the state of the oscillating signal at the time an applied voltage reaches the threshold voltage may likewise vary in a statistically random manner, and thus the corresponding logic value that is output may be a random value suitable for random number generation.
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公开(公告)号：US12033695B2
公开(公告)日：2024-07-09
申请号：US17740062
申请日：2022-05-09
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Alessandro Sebastiani , Mattia Robustelli , Matteo Impalà
CPC classification number: G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C13/0097 , G11C2013/0073 , G11C2013/0078 , G11C2013/0092
Abstract: Methods, systems, and devices for improved techniques for multi-level memory cell programming are described. A memory array may receive a first command to store a first logic state in a memory cell for storing three or more logic states. The memory array may apply, as part of an erase operation, a first pulse with a first polarity to a plurality of memory cells to store a second logic state different from the first logic state in the plurality of memory cells, where the plurality of memory cells includes the memory cell. The memory array may apply, as part of a write operation or as part of the erase operation, one or more second pulses with a second polarity to the memory cell to store the first logic state in the memory cell based on applying the first pulse.
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公开(公告)号：US20230360699A1
公开(公告)日：2023-11-09
申请号：US17740062
申请日：2022-05-09
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Alessandro Sebastiani , Mattia Robustelli , Matteo Impalà
CPC classification number: G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C13/0097
Abstract: Methods, systems, and devices for improved techniques for multi-level memory cell programming are described. A memory array may receive a first command to store a first logic state in a memory cell for storing three or more logic states. The memory array may apply, as part of an erase operation, a first pulse with a first polarity to a plurality of memory cells to store a second logic state different from the first logic state in the plurality of memory cells, where the plurality of memory cells includes the memory cell. The memory array may apply, as part of a write operation or as part of the erase operation, one or more second pulses with a second polarity to the memory cell to store the first logic state in the memory cell based on applying the first pulse.
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