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公开(公告)号：US20240221829A1
公开(公告)日：2024-07-04
申请号：US18409992
申请日：2024-01-11
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Fabio Pellizzer , Mattia Robustelli , Alessandro Sebastiani
IPC: G11C13/00
CPC classification number: G11C13/003 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C13/0069 , G11C2213/71
Abstract: Methods, systems, and devices for a cross-point pillar architecture for memory arrays are described. Multiple selector devices may be configured to access or activate a pillar within a memory array, where the selector devices may each be or include a chalcogenide material. A pillar access line may be coupled with multiple selector devices, where each selector device may correspond to a pillar associated with the pillar access line. Pillar access lines on top and bottom of the pillars of the memory array may be aligned in a square or rectangle formation, or in a hexagonal formation. Pillars and corresponding selector devices on top and bottom of the pillars may be located at overlapping portions of the pillar access lines, thereby forming a cross point architecture for pillar selection or activation. The selector devices may act in pairs to select or activate a pillar upon application of a respective selection voltage.
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公开(公告)号：US11887661B2
公开(公告)日：2024-01-30
申请号：US17647578
申请日：2022-01-10
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Fabio Pellizzer , Mattia Robustelli , Alessandro Sebastiani
IPC: G11C13/00
CPC classification number: G11C13/003 , G11C13/0004 , G11C13/004 , G11C13/0023 , G11C13/0069 , G11C2213/71
Abstract: Methods, systems, and devices for a cross-point pillar architecture for memory arrays are described. Multiple selector devices may be configured to access or activate a pillar within a memory array, where the selector devices may each be or include a chalcogenide material. A pillar access line may be coupled with multiple selector devices, where each selector device may correspond to a pillar associated with the pillar access line. Pillar access lines on top and bottom of the pillars of the memory array may be aligned in a square or rectangle formation, or in a hexagonal formation. Pillars and corresponding selector devices on top and bottom of the pillars may be located at overlapping portions of the pillar access lines, thereby forming a cross point architecture for pillar selection or activation. The selector devices may act in pairs to select or activate a pillar upon application of a respective selection voltage.
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公开(公告)号：US20220415409A1
公开(公告)日：2022-12-29
申请号：US17361194
申请日：2021-06-28
Applicant: Micron Technology, Inc.
Inventor： Alessandro Sebastiani , Innocenzo Tortorelli
Abstract: Methods, systems, and devices for programming techniques for polarity-based memory cells are described. A method may include writing memory cells to an intermediate state based on receiving a write command. Writing the intermediate state may include applying a first pulse having a first polarity to the memory cell. The method may include isolating a first access line coupled with the memory cell from a voltage source based on applying the first pulse. The method may also include applying a second pulse to a second access line coupled with the memory cell based on isolating the first access line.
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公开(公告)号：US12283316B2
公开(公告)日：2025-04-22
申请号：US18409992
申请日：2024-01-11
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Fabio Pellizzer , Mattia Robustelli , Alessandro Sebastiani
IPC: G11C13/00
Abstract: Methods, systems, and devices for a cross-point pillar architecture for memory arrays are described. Multiple selector devices may be configured to access or activate a pillar within a memory array, where the selector devices may each be or include a chalcogenide material. A pillar access line may be coupled with multiple selector devices, where each selector device may correspond to a pillar associated with the pillar access line. Pillar access lines on top and bottom of the pillars of the memory array may be aligned in a square or rectangle formation, or in a hexagonal formation. Pillars and corresponding selector devices on top and bottom of the pillars may be located at overlapping portions of the pillar access lines, thereby forming a cross point architecture for pillar selection or activation. The selector devices may act in pairs to select or activate a pillar upon application of a respective selection voltage.
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公开(公告)号：US20230207002A1
公开(公告)日：2023-06-29
申请号：US17647578
申请日：2022-01-10
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Fabio Pellizzer , Mattia Robustelli , Alessandro Sebastiani
IPC: G11C13/00
CPC classification number: G11C13/003 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C13/0069 , G11C2213/71
Abstract: Methods, systems, and devices for a cross-point pillar architecture for memory arrays are described. Multiple selector devices may be configured to access or activate a pillar within a memory array, where the selector devices may each be or include a chalcogenide material. A pillar access line may be coupled with multiple selector devices, where each selector device may correspond to a pillar associated with the pillar access line. Pillar access lines on top and bottom of the pillars of the memory array may be aligned in a square or rectangle formation, or in a hexagonal formation. Pillars and corresponding selector devices on top and bottom of the pillars may be located at overlapping portions of the pillar access lines, thereby forming a cross point architecture for pillar selection or activation. The selector devices may act in pairs to select or activate a pillar upon application of a respective selection voltage.
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Patent Agency Ranking
公开(公告)号：US20240404590A1
公开(公告)日：2024-12-05
申请号：US18742753
申请日：2024-06-13
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Alessandro Sebastiani , Mattia Robustelli , Matteo Impalà
Abstract: Methods, systems, and devices for improved techniques for multi-level memory cell programming are described. A memory array may receive a first command to store a first logic state in a memory cell for storing three or more logic states. The memory array may apply, as part of an erase operation, a first pulse with a first polarity to a plurality of memory cells to store a second logic state different from the first logic state in the plurality of memory cells, where the plurality of memory cells includes the memory cell. The memory array may apply, as part of a write operation or as part of the erase operation, one or more second pulses with a second polarity to the memory cell to store the first logic state in the memory cell based on applying the first pulse.
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公开(公告)号：US12033695B2
公开(公告)日：2024-07-09
申请号：US17740062
申请日：2022-05-09
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Alessandro Sebastiani , Mattia Robustelli , Matteo Impalà
CPC classification number: G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C13/0097 , G11C2013/0073 , G11C2013/0078 , G11C2013/0092
Abstract: Methods, systems, and devices for improved techniques for multi-level memory cell programming are described. A memory array may receive a first command to store a first logic state in a memory cell for storing three or more logic states. The memory array may apply, as part of an erase operation, a first pulse with a first polarity to a plurality of memory cells to store a second logic state different from the first logic state in the plurality of memory cells, where the plurality of memory cells includes the memory cell. The memory array may apply, as part of a write operation or as part of the erase operation, one or more second pulses with a second polarity to the memory cell to store the first logic state in the memory cell based on applying the first pulse.
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公开(公告)号：US20240029796A1
公开(公告)日：2024-01-25
申请号：US17868750
申请日：2022-07-19
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Mattia Robustelli , Alessandro Sebastiani , Matteo Impala' , Fabio Pellizzer
CPC classification number: G11C16/102 , G11C16/20 , G11C16/0425
Abstract: Systems, methods, and apparatuses are provided for unipolar programming of memory cells in a semiconductor device. A memory has a plurality of self-selecting memory cells and circuitry configured to program a self-selecting memory cell of the plurality of self-selecting memory cells to a first data state or a second data state by applying a current pulse to the self-selecting memory cell. The current is a set pulse or a reset pulse. The set pulse and the reset pulse have a same polarity.
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公开(公告)号：US20230360699A1
公开(公告)日：2023-11-09
申请号：US17740062
申请日：2022-05-09
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Alessandro Sebastiani , Mattia Robustelli , Matteo Impalà
CPC classification number: G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C13/0097
Abstract: Methods, systems, and devices for improved techniques for multi-level memory cell programming are described. A memory array may receive a first command to store a first logic state in a memory cell for storing three or more logic states. The memory array may apply, as part of an erase operation, a first pulse with a first polarity to a plurality of memory cells to store a second logic state different from the first logic state in the plurality of memory cells, where the plurality of memory cells includes the memory cell. The memory array may apply, as part of a write operation or as part of the erase operation, one or more second pulses with a second polarity to the memory cell to store the first logic state in the memory cell based on applying the first pulse.
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公开(公告)号：US11735276B2
公开(公告)日：2023-08-22
申请号：US17361194
申请日：2021-06-28
Applicant: Micron Technology, Inc.
Inventor： Alessandro Sebastiani , Innocenzo Tortorelli
CPC classification number: G11C16/30 , G11C16/08 , G11C16/26 , G11C16/32 , G11C16/3404
Abstract: Methods, systems, and devices for programming techniques for polarity-based memory cells are described. A method may include writing memory cells to an intermediate state based on receiving a write command. Writing the intermediate state may include applying a first pulse having a first polarity to the memory cell. The method may include isolating a first access line coupled with the memory cell from a voltage source based on applying the first pulse. The method may also include applying a second pulse to a second access line coupled with the memory cell based on isolating the first access line.
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