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1.
公开(公告)号:US20190189576A1
公开(公告)日:2019-06-20
申请号:US16276533
申请日:2019-02-14
Applicant: Micron Technology, Inc.
Inventor: Mayukhee Das , Jonathan S. Hacker , Christopher J. Gambee , Chandra S. Tiwari
IPC: H01L23/00 , H01L21/66 , H01L25/065
CPC classification number: H01L24/05 , H01L22/32 , H01L24/03 , H01L24/11 , H01L24/13 , H01L25/0657 , H01L2224/03011 , H01L2224/0345 , H01L2224/03921 , H01L2224/0401 , H01L2224/05017 , H01L2224/05082 , H01L2224/05124 , H01L2224/05166 , H01L2224/05186 , H01L2224/05624 , H01L2224/05647 , H01L2224/1146 , H01L2224/11849 , H01L2224/13014 , H01L2224/13021 , H01L2224/13026 , H01L2224/13147 , H01L2224/16145 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/0652 , H01L2924/01022 , H01L2924/01029 , H01L2924/00014 , H01L2924/04941 , H01L2924/01074
Abstract: Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond pad having a bonding surface with a process artifact. A passivation material can be positioned to at least partially fill a portion of the process artifact. A conductive structure can be positioned to extend across the bonding surface of the bond pad.
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公开(公告)号:US10262961B2
公开(公告)日:2019-04-16
申请号:US15982129
申请日:2018-05-17
Applicant: Micron Technology, Inc.
Inventor: Mayukhee Das , Jonathan S. Hacker , Christopher J. Gambee , Chandra S. Tiwari
IPC: H01L23/00 , H01L25/065 , H01L21/66
Abstract: Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond pad having a bonding surface with a process artifact. A passivation material can be positioned to at least partially fill a portion of the process artifact. A conductive structure can be positioned to extend across the bonding surface of the bond pad.
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3.
公开(公告)号:US20190051623A1
公开(公告)日:2019-02-14
申请号:US15982129
申请日:2018-05-17
Applicant: Micron Technology, Inc.
Inventor: Mayukhee Das , Jonathan S. Hacker , Christopher J. Gambee , Chandra S. Tiwari
IPC: H01L23/00 , H01L25/065 , H01L21/66
Abstract: Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond pad having a bonding surface with a process artifact. A passivation material can be positioned to at least partially fill a portion of the process artifact. A conductive structure can be positioned to extend across the bonding surface of the bond pad.
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公开(公告)号:US10896886B2
公开(公告)日:2021-01-19
申请号:US16276533
申请日:2019-02-14
Applicant: Micron Technology, Inc.
Inventor: Mayukhee Das , Jonathan S. Hacker , Christopher J. Gambee , Chandra S. Tiwari
IPC: H01L23/00 , H01L21/66 , H01L25/065
Abstract: Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond pad having a bonding surface with a process artifact. A passivation material can be positioned to at least partially fill a portion of the process artifact. A conductive structure can be positioned to extend across the bonding surface of the bond pad.
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公开(公告)号:US10002840B1
公开(公告)日:2018-06-19
申请号:US15672006
申请日:2017-08-08
Applicant: Micron Technology, Inc.
Inventor: Mayukhee Das , Jonathan S. Hacker , Christopher J. Gambee , Chandra S. Tiwari
IPC: H01L23/00 , H01L21/66 , H01L25/065
CPC classification number: H01L24/05 , H01L22/32 , H01L24/03 , H01L24/11 , H01L24/13 , H01L25/0657 , H01L2224/03011 , H01L2224/0345 , H01L2224/03921 , H01L2224/0401 , H01L2224/05017 , H01L2224/05082 , H01L2224/05124 , H01L2224/05166 , H01L2224/05186 , H01L2224/05624 , H01L2224/05647 , H01L2224/1146 , H01L2224/11849 , H01L2224/13014 , H01L2224/13021 , H01L2224/13026 , H01L2224/13147 , H01L2224/16145 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/0652 , H01L2924/01022 , H01L2924/01029 , H01L2924/00014 , H01L2924/04941 , H01L2924/01074
Abstract: Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond pad having a bonding surface with a process artifact. A passivation material can be positioned to at least partially fill a portion of the process artifact. A conductive structure can be positioned to extend across the bonding surface of the bond pad, and a conductive interconnect can extend from the conductive structure.
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