公开(公告)号：US11848070B2

公开(公告)日：2023-12-19

申请号：US17523312

申请日：2021-11-10

Applicant: Micron Technology, Inc.

Inventor： Mijo Kim ,  Scott E. Smith ,  Si Hong Kim

IPC: G11C7/10 ,  G11C8/18 ,  G11C7/20

CPC classification number: G11C7/1093 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/20 ,  G11C8/18

Abstract: Memory with DQS pulse control circuitry is disclosed herein. In one embodiment, a memory device comprises a DQS terminal and circuitry operably coupled to the DQS terminal. The DQS terminal is configured to receive an external DQS signal including a first pulse having a first width. In turn, the circuitry is configured to generate a second pulse based at least in part on the first pulse and output an internal DQS signal including the second pulse. The second pulse can have a second width greater than the first width. In some embodiments, the external DQS signal can further include a third pulse having a third width greater than the second width. In such embodiments, the circuitry can be further configured to generate and output a fourth pulse based at least in part on the third pulse that has a fourth width equivalent to the third width.

公开(公告)号：US11740795B2

公开(公告)日：2023-08-29

申请号：US17721160

申请日：2022-04-14

Applicant: Micron Technology, Inc.

Inventor： Suryanarayana B. Tatapudi ,  John David Porter ,  Jaeil Kim ,  Mijo Kim

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/10

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0676 ,  G06F3/0679 ,  G06F13/1668 ,  G11C7/10 ,  G06F2213/16

Abstract: Techniques for configurable link interfaces for a memory device are described. In some examples, memory devices may require periodic link training to support data transfer with a host device at relatively fast rates. However, in some managed memory applications, memory dies of a memory device may have integrated controllers that do not support such link training, and accordingly may not support some clock rates or data rates. To support data transfers between a host device and a memory device at relatively fast clock rates or data rates without link training, a memory die may be fabricated with a configurable link interface that can support different mappings between components and operation according to different clock rates or data rates. In some examples, a memory die may be fabricated in a manner that supports configurable mappings between an array and a data channel interface that are operable according to different multiplexing and serialization.

公开(公告)号：US20220011934A1

公开(公告)日：2022-01-13

申请号：US16925773

申请日：2020-07-10

Applicant: Micron Technology, Inc.

Inventor： Suryanarayana B. Tatapudi ,  John David Porter ,  Jaeil Kim ,  Mijo Kim

IPC: G06F3/06 ,  G06F13/16

Abstract: Techniques for configurable link interfaces for a memory device are described. In some examples, memory devices may require periodic link training to support data transfer with a host device at relatively fast rates. However, in some managed memory applications, memory dies of a memory device may have integrated controllers that do not support such link training, and accordingly may not support some clock rates or data rates. To support data transfers between a host device and a memory device at relatively fast clock rates or data rates without link training, a memory die may be fabricated with a configurable link interface that can support different mappings between components and operation according to different clock rates or data rates. In some examples, a memory die may be fabricated in a manner that supports configurable mappings between an array and a data channel interface that are operable according to different multiplexing and serialization.

公开(公告)号：US20230146544A1

公开(公告)日：2023-05-11

申请号：US17523312

申请日：2021-11-10

Applicant: Micron Technology, Inc.

Inventor： Mijo Kim ,  Scott E. Smith ,  Si Hong Kim

IPC: G11C7/10 ,  G11C7/20 ,  G11C8/18

CPC classification number: G11C7/1093 ,  G11C7/1066 ,  G11C7/20 ,  G11C7/106 ,  G11C7/1087 ,  G11C8/18

Abstract: Memory with DQS pulse control circuitry is disclosed herein. In one embodiment, a memory device comprises a DQS terminal and circuitry operably coupled to the DQS terminal. The DQS terminal is configured to receive an external DQS signal including a first pulse having a first width. In turn, the circuitry is configured to generate a second pulse based at least in part on the first pulse and output an internal DQS signal including the second pulse. The second pulse can have a second width greater than the first width. In some embodiments, the external DQS signal can further include a third pulse having a third width greater than the second width. In such embodiments, the circuitry can be further configured to generate and output a fourth pulse based at least in part on the third pulse that has a fourth width equivalent to the third width.

公开(公告)号：US20220308757A1

公开(公告)日：2022-09-29

申请号：US17721160

申请日：2022-04-14

Applicant: Micron Technology, Inc.

Inventor： Suryanarayana B. Tatapudi ,  John David Porter ,  Jaeil Kim ,  Mijo Kim

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/10

Abstract: Techniques for configurable link interfaces for a memory device are described. In some examples, memory devices may require periodic link training to support data transfer with a host device at relatively fast rates. However, in some managed memory applications, memory dies of a memory device may have integrated controllers that do not support such link training, and accordingly may not support some clock rates or data rates. To support data transfers between a host device and a memory device at relatively fast clock rates or data rates without link training, a memory die may be fabricated with a configurable link interface that can support different mappings between components and operation according to different clock rates or data rates. In some examples, a memory die may be fabricated in a manner that supports configurable mappings between an array and a data channel interface that are operable according to different multiplexing and serialization.

公开(公告)号：US11307771B2

公开(公告)日：2022-04-19

申请号：US16925773

申请日：2020-07-10

Applicant: Micron Technology, Inc.

Inventor： Suryanarayana B. Tatapudi ,  John David Porter ,  Jaeil Kim ,  Mijo Kim

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/10

Abstract: Techniques for configurable link interfaces for a memory device are described. In some examples, memory devices may require periodic link training to support data transfer with a host device at relatively fast rates. However, in some managed memory applications, memory dies of a memory device may have integrated controllers that do not support such link training, and accordingly may not support some clock rates or data rates. To support data transfers between a host device and a memory device at relatively fast clock rates or data rates without link training, a memory die may be fabricated with a configurable link interface that can support different mappings between components and operation according to different clock rates or data rates. In some examples, a memory die may be fabricated in a manner that supports configurable mappings between an array and a data channel interface that are operable according to different multiplexing and serialization.