公开(公告)号：US20230297285A1

公开(公告)日：2023-09-21

申请号：US18121874

申请日：2023-03-15

Applicant: Micron Technology, Inc.

Inventor： Amitava Majumdar ,  Anandhavel Nagendrakumar ,  Mohammed Ebrahim Hargan ,  Scott Garner ,  Danilo Caraccio ,  Daniele Balluchi ,  Chia Wei Chang ,  Ankush Lal

IPC: G06F3/06 ,  G11C11/406

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0673 ,  G11C11/406

Abstract: An apparatus can include a number of memory devices and a memory controller coupled to one or more of the number of memory devices. The memory controller can include a row hammer detector. The memory controller can be configured increment for a first time period a row counter in a first data structure and a refresh counter. The memory controller can be configured to increment for a second time period a row counter in a second data structure and the refresh counter. The memory controller can be configured to determine that a value of the refresh counter exceeds a refresh threshold and responsive to the determination that the value of the refresh counter exceeds the refresh threshold, issue a notification.

公开(公告)号：US20250053343A1

公开(公告)日：2025-02-13

申请号：US18929332

申请日：2024-10-28

Applicant: Micron Technology, Inc.

Inventor： Amitava Majumdar ,  Anandhavel Nagendrakumar ,  Mohammed Ebrahim Hargan ,  Scott Garner ,  Danilo Caraccio ,  Daniele Balluchi ,  Chia Wei Chang ,  Ankush Lal

IPC: G06F3/06 ,  G11C11/406

Abstract: An apparatus can include a number of memory devices and a memory controller coupled to one or more of the number of memory devices. The memory controller can include a row hammer detector. The memory controller can be configured increment for a first time period a row counter in a first data structure and a refresh counter. The memory controller can be configured to increment for a second time period a row counter in a second data structure and the refresh counter. The memory controller can be configured to determine that a value of the refresh counter exceeds a refresh threshold and responsive to the determination that the value of the refresh counter exceeds the refresh threshold, issue a notification.

公开(公告)号：US12170531B2

公开(公告)日：2024-12-17

申请号：US17896994

申请日：2022-08-26

Applicant: Micron Technology, Inc.

Inventor： Joseph M. McCrate ,  Nevil Gajera ,  Mohammed Ebrahim Hargan

IPC: H03M13/15 ,  H03M13/37

Abstract: Provided is a memory system comprising an error correction code (ECC) decoder configured to receive data from a memory. The ECC decoder includes a syndrome generator configured to calculate at least one of syndrome vector and an erasure value, the calculation being devoid of erasure location information and an error-location polynomial generator configured to determine error location and error/erasure value polynomials responsive to syndrome and erasure calculation values output from the syndrome generator. An error value generator confirms error values at one or more known error locations based upon the determined error/erasure value polynomials, and an error location generator search for an error evaluation value to confirm the known error locations based upon the determined error location polynomials. Outputs of the error value generator and the error location generator are combined to produce corrected data.

公开(公告)号：US12131071B2

公开(公告)日：2024-10-29

申请号：US18121874

申请日：2023-03-15

Applicant: Micron Technology, Inc.

Inventor： Amitava Majumdar ,  Anandhavel Nagendrakumar ,  Mohammed Ebrahim Hargan ,  Scott Garner ,  Danilo Caraccio ,  Daniele Balluchi ,  Chia Wei Chang ,  Ankush Lal

IPC: G06F3/06 ,  G11C11/406

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0673 ,  G11C11/406

Abstract: An apparatus can include a number of memory devices and a memory controller coupled to one or more of the number of memory devices. The memory controller can include a row hammer detector. The memory controller can be configured increment for a first time period a row counter in a first data structure and a refresh counter. The memory controller can be configured to increment for a second time period a row counter in a second data structure and the refresh counter. The memory controller can be configured to determine that a value of the refresh counter exceeds a refresh threshold and responsive to the determination that the value of the refresh counter exceeds the refresh threshold, issue a notification.

公开(公告)号：US20240413842A1

公开(公告)日：2024-12-12

申请号：US18608627

申请日：2024-03-18

Applicant: Micron Technology, Inc.

Inventor： Joseph M. McCrate ,  Nevil Gajera ,  Mohammed Ebrahim Hargan

IPC: H03M13/15 ,  H03M13/37

Abstract: Provided is a memory system comprising a plurality of memory components; and a controller in communication with the plurality of memory components and configured to perform error correction code (ECC) decoding on a received word read from the plurality of memory components. The ECC decoding is configured to (i) detect one or more random errors in a portion of the received word, the portion corresponding to one of the components within the plurality, and (ii) correct the detected random errors; and when the correcting of the detected random errors fails, iteratively marking symbols in the remaining portions of the received word as erasures.

公开(公告)号：US11962327B2

公开(公告)日：2024-04-16

申请号：US17896957

申请日：2022-08-26

Applicant: Micron Technology, Inc.

Inventor： Joseph M. McCrate ,  Nevil Gajera ,  Mohammed Ebrahim Hargan

IPC: H03M13/15 ,  H03M13/37

CPC classification number: H03M13/154 ,  H03M13/1575 ,  H03M13/153 ,  H03M13/1545 ,  H03M13/373 ,  H03M13/3746

Abstract: Provided is a memory system comprising a plurality of memory components; and a controller in communication with the plurality of memory components and configured to perform error correction code (ECC) decoding on a received word read from the plurality of memory components. The ECC decoding is configured to (i) detect one or more random errors in a portion of the received word, the portion corresponding to one of the components within the plurality, and (ii) correct the detected random errors; and when the correcting of the detected random errors fails, iteratively marking symbols in the remaining portions of the received word as erasures.

公开(公告)号：US20230223961A1

公开(公告)日：2023-07-13

申请号：US17896994

申请日：2022-08-26

Applicant: Micron Technology, Inc.

Inventor： Joseph M. McCrate ,  Nevil Gajera ,  Mohammed Ebrahim Hargan

IPC: H03M13/37 ,  H03M13/15

CPC classification number: H03M13/373 ,  H03M13/153 ,  H03M13/154 ,  H03M13/1545 ,  H03M13/1575 ,  H03M13/3746

Abstract: Provided is a memory system comprising an error correction code (ECC) decoder configured to receive data from a memory. The ECC decoder includes a syndrome generator configured to calculate at least one of syndrome vector and an erasure value, the calculation being devoid of erasure location information and an error-location polynomial generator configured to determine error location and error/erasure value polynomials responsive to syndrome and erasure calculation values output from the syndrome generator. An error value generator confirms error values at one or more known error locations based upon the determined error/erasure value polynomials, and an error location generator search for an error evaluation value to confirm the known error locations based upon the determined error location polynomials. Outputs of the error value generator and the error location generator are combined to produce corrected data.

公开(公告)号：US20230223960A1

公开(公告)日：2023-07-13

申请号：US17896957

申请日：2022-08-26

Applicant: Micron Technology, Inc.

Inventor： Joseph M. McCrate ,  Nevil Gajera ,  Mohammed Ebrahim Hargan

IPC: H03M13/37

CPC classification number: H03M13/373 ,  H03M13/3746

Abstract: Provided is a memory system comprising a plurality of memory components; and a controller in communication with the plurality of memory components and configured to perform error correction code (ECC) decoding on a received word read from the plurality of memory components. The ECC decoding is configured to (i) detect one or more random errors in a portion of the received word, the portion corresponding to one of the components within the plurality, and (ii) correct the detected random errors; and when the correcting of the detected random errors fails, iteratively marking symbols in the remaining portions of the received word as erasures.