公开(公告)号：US20250117322A1

公开(公告)日：2025-04-10

申请号：US18776215

申请日：2024-07-17

Applicant: Micron Technology, Inc.

Inventor： Ritesh Tiwari ,  Giuseppe Cariello

IPC: G06F12/02

Abstract: Methods, systems, and devices for segregating logical to physical mappings are described. A memory system may segregate L2P mappings based on one or more characteristics of the data associated with to the L2P mappings. The memory system may determine whether a logical address included in a write command is associated with a first characteristic, a second characteristic, or some other characteristic. The memory system may write an L2P mapping to a first block of memory cells, a second block of memory cells, or some other block of memory cells based on the determined characteristic of the L2P mapping. The block of memory cells that the L2P mapping is written to may include other mappings having data with a same (or similar) characteristic.

公开(公告)号：US20240289272A1

公开(公告)日：2024-08-29

申请号：US18444421

申请日：2024-02-16

Applicant: Micron Technology, Inc.

Inventor： Ritesh Tiwari ,  Giuseppe Cariello

IPC: G06F12/02 ,  G06F12/0882

CPC classification number: G06F12/0246 ,  G06F12/0882 ,  G06F2212/7201

Abstract: Methods, systems, and devices for systems and techniques for updating logical-to-physical (L2P) mappings are described. A memory system may support improved change log entries that supports a change log entry to indicate updated L2P mapping information for multiple data chunks, thus increasing the amount of data indicated by the change log before it becomes full. One change log entry may be used to indicate updated L2P information for multiple sequential data chunks. For example, the memory system may write data to a set of contiguous data chunks of a non-volatile memory device. The memory system may write a change log entry to a change log that includes updated L2P mapping information for the set of data chunks by including at least a first indication of a virtual block that includes the data chunks and a second indication of the quantity of data chunks in the set.

公开(公告)号：US20240176491A1

公开(公告)日：2024-05-30

申请号：US18504992

申请日：2023-11-08

Applicant: Micron Technology, Inc.

Inventor： Sridhar Prudviraj Gunda ,  Amiya Banerjee ,  Ritesh Tiwari ,  Shreesha Prabhu

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673

Abstract: Methods, systems, and devices for an erase operation for a memory system are described. The memory system may perform, on a block of memory cells, a first portion of an erase operation. After performing the first portion of the erase operation, the memory system may receive a write command to write data to the block of memory cells. In response to receiving the write command, the memory system may determine whether a threshold voltage of the block of memory cells satisfies a threshold. In response to determining the that the threshold voltage satisfies the threshold, the memory system may perform a second portion of the erase operation on the block of memory cells. As such, the memory system may write the data to the block of memory cells in response to performing the second portion of the erase operation.

公开(公告)号：US20240281383A1

公开(公告)日：2024-08-22

申请号：US18431544

申请日：2024-02-02

Applicant: Micron Technology, Inc.

Inventor： Ritesh Tiwari ,  Sridhar Prudviraj Gunda ,  Giuseppe Cariello

IPC: G06F12/1027 ,  G06F12/0873

CPC classification number: G06F12/1027 ,  G06F12/0873

Abstract: Methods, systems, and devices for buffer expansion for random write operations are described. Implementations provide buffer expansion for random write operations used to store L2P address translation table data under certain recognized operation workloads. Memory locations within the memory system controller are typically allocated for use during various operations. During different operational workloads, the amount of memory required for each of these different allocated memory areas may vary. By recognizing the entry of the memory system into a workload of random write operations, the memory system controller may expand a buffer size used to store the portion of the L2P address translation table data used during the write operations to retain larger portions of the L2P address translation table in the buffer.

公开(公告)号：US20240281254A1

公开(公告)日：2024-08-22

申请号：US18581273

申请日：2024-02-19

Applicant: Micron Technology, Inc.

Inventor： Sridhar Prudviraj Gunda ,  Mani Raghavendra Aravapalli ,  Ritesh Tiwari

IPC: G06F9/30

CPC classification number: G06F9/30185

Abstract: Methods, systems, and devices for overlay code retrieval from a host system are described. A memory system may determine that a set of code for execution by a processor of the memory system is absent from an executable memory of the processor. The memory system may prevent the processor from retrieving the set of code from a non-volatile memory of the memory system based on the set of code being designated for retrieval from a host system. The memory system may retrieve the set of code from a memory of a host system, instead of retrieving the set of code from the non-volatile memory, based on the set of code being designated for retrieval from the host system.

公开(公告)号：US20240160352A1

公开(公告)日：2024-05-16

申请号：US18506874

申请日：2023-11-10

Applicant: Micron Technology, Inc.

Inventor： Ritesh Tiwari ,  Sridhar Prudviraj Gunda ,  Jameer Mulani

IPC: G06F3/06 ,  G06F12/1009

CPC classification number: G06F3/0611 ,  G06F3/0647 ,  G06F3/0679 ,  G06F12/1009

Abstract: Methods, systems, and devices for memory cell folding operations using host system memory are described. A memory system may temporarily store data to host system memory as part of a data transfer operation. For example, the memory system may transfer respective portions of data from a first non-volatile memory device to a first volatile memory device of the memory system and transfer the respective portions of data to a second volatile memory device of the host system based on a storage capacity of the first volatile memory device. The second volatile memory device may accumulate the portions of data until an aggregate size of the data satisfies a threshold, and the host system may transmit the aggregate data to be written to a second non-volatile memory device of the memory system.