公开(公告)号：US20150364400A1

公开(公告)日：2015-12-17

申请号：US14307148

申请日：2014-06-17

Applicant: Micron Technology, Inc.

Inventor： Ross S. Dando

IPC: H01L23/48 ,  H01L23/36 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/76898 ,  H01L23/36 ,  H01L25/065 ,  H01L2224/16145 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure comprises conductive vias extending from an active surface of a substrate to a back side of the substrate and surrounded by a dielectric material. The conductive vias are surrounded by recessed isolation structures formed within the back side of the substrate. Conductive elements extend over the conductive vias and laterally over at least portions of the isolation structures. The conductive elements are in electrical contact with the conductive vias and electrically isolated from the substrate by the isolation structures. Thermally conductive elements in contact with the substrate are laterally spaced from the conductive elements. Die assemblies comprising the semiconductor structure, methods of forming the semiconductor structure, and methods of forming the die assemblies are also disclosed.

Abstract translation: 半导体结构包括从衬底的有源表面延伸到衬底的背面并被电介质材料包围的导电通孔。 导电通孔被形成在衬底的背面内的凹陷的隔离结构包围。 导电元件在导电通孔之上延伸并且在隔离结构的至少部分上横向延伸。 导电元件与导电通孔电接触并通过隔离结构与衬底电隔离。 与基板接触的导热元件与导电元件横向间隔开。 还公开了包括半导体结构的模具组件，形成半导体结构的方法以及形成模具组件的方法。

公开(公告)号：US20150247236A1

公开(公告)日：2015-09-03

申请号：US14699830

申请日：2015-04-29

Applicant: Micron Technology, Inc.

Inventor： Ross S. Dando ,  F. Daniel Gealy

IPC: C23C16/04 ,  C23C16/455 ,  C23C16/48 ,  C23C16/52

CPC classification number: C23C16/047 ,  C23C16/45525 ,  C23C16/483 ,  C23C16/52

Abstract: Methods for depositing material onto microfeature workpieces in reaction chambers and systems for depositing materials onto microfeature workpieces are disclosed herein. In one embodiment, a method includes depositing molecules of a gas onto a microfeature workpiece in the reaction chamber and selectively irradiating a first portion of the molecules on the microfeature workpiece in the reaction chamber with a selected radiation without irradiating a second portion of the molecules on the workpiece with the selected radiation. The first portion of the molecules can be irradiated to activate the portion of the molecules or desorb the portion of the molecules from the workpiece. The first portion of the molecules can be selectively irradiated by impinging the first portion of the molecules with a laser beam or other energy source.

Abstract translation: 本文公开了在反应室中的微型工件上沉积材料的方法和用于将材料沉积到微特征工件上的系统。 在一个实施方案中，一种方法包括将气体的分子沉积到反应室中的微特征工件上，并用选定的辐射选择性地照射反应室中的微特征工件上的分子的第一部分，而不会将分子的第二部分 工件与选定的辐射。 可以照射分子的第一部分以激活分子的一部分或从工件解吸部分分子。 分子的第一部分可以通过用激光束或其他能量源撞击分子的第一部分来选择性地照射。

公开(公告)号：US12014958B2

公开(公告)日：2024-06-18

申请号：US18047049

申请日：2022-10-17

Applicant: Micron Technology, Inc.

Inventor： William M. Hiatt ,  Ross S. Dando

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5384 ,  H01L2224/13025

Abstract: Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. The microfeature workpieces may have a terminal and a substrate with a first side carrying the terminal and a second side opposite the first side. In one embodiment, a method includes (a) constructing an electrically conductive interconnect extending from the terminal to at least an intermediate depth in the substrate with the interconnect electrically connected to the terminal, and (b) removing material from the second side of the substrate so that a portion of the interconnect projects from the substrate.

公开(公告)号：US11476160B2

公开(公告)日：2022-10-18

申请号：US16991965

申请日：2020-08-12

Applicant: Micron Technology, Inc.

Inventor： William M. Hiatt ,  Ross S. Dando

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538

Abstract: Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. The microfeature workpieces may have a terminal and a substrate with a first side carrying the terminal and a second side opposite the first side. In one embodiment, a method includes (a) constructing an electrically conductive interconnect extending from the terminal to at least an intermediate depth in the substrate with the interconnect electrically connected to the terminal, and (b) removing material from the second side of the substrate so that a portion of the interconnect projects from the substrate.

公开(公告)号：US20240339360A1

公开(公告)日：2024-10-10

申请号：US18744493

申请日：2024-06-14

Applicant: Micron Technology, Inc.

Inventor： William M. Hiatt ,  Ross S. Dando

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5384 ,  H01L2224/13025

Abstract: Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. The microfeature workpieces may have a terminal and a substrate with a first side carrying the terminal and a second side opposite the first side. In one embodiment, a method includes (a) constructing an electrically conductive interconnect extending from the terminal to at least an intermediate depth in the substrate with the interconnect electrically connected to the terminal, and (b) removing material from the second side of the substrate so that a portion of the interconnect projects from the substrate.

公开(公告)号：US20210005514A1

公开(公告)日：2021-01-07

申请号：US16991965

申请日：2020-08-12

Applicant: Micron Technology, Inc.

Inventor： William M. Hiatt ,  Ross S. Dando

IPC: H01L21/768 ,  H01L23/48

Abstract: Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. The microfeature workpieces may have a terminal and a substrate with a first side carrying the terminal and a second side opposite the first side. In one embodiment, a method includes (a) constructing an electrically conductive interconnect extending from the terminal to at least an intermediate depth in the substrate with the interconnect electrically connected to the terminal, and (b) removing material from the second side of the substrate so that a portion of the interconnect projects from the substrate.

公开(公告)号：US20170323828A1

公开(公告)日：2017-11-09

申请号：US15662204

申请日：2017-07-27

Applicant: Micron Technology, Inc.

Inventor： William M. Hiatt ,  Ross S. Dando

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2224/13025

Abstract: Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. The microfeature workpieces may have a terminal and a substrate with a first side carrying the terminal and a second side opposite the first side. In one embodiment, a method includes (a) constructing an electrically conductive interconnect extending from the terminal to at least an intermediate depth in the substrate with the interconnect electrically connected to the terminal, and (b) removing material from the second side of the substrate so that a portion of the interconnect projects from the substrate.

公开(公告)号：US09653381B2

公开(公告)日：2017-05-16

申请号：US14307148

申请日：2014-06-17

Applicant: Micron Technology, Inc.

Inventor： Ross S. Dando

IPC: H01L23/48 ,  H01L21/768 ,  H01L25/065 ,  H01L21/762 ,  H01L23/36

CPC classification number: H01L23/481 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/76898 ,  H01L23/36 ,  H01L25/065 ,  H01L2224/16145 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure comprises conductive vias extending from an active surface of a substrate to a back side of the substrate and surrounded by a dielectric material. The conductive vias are surrounded by recessed isolation structures formed within the back side of the substrate. Conductive elements extend over the conductive vias and laterally over at least portions of the isolation structures. The conductive elements are in electrical contact with the conductive vias and electrically isolated from the substrate by the isolation structures. Thermally conductive elements in contact with the substrate are laterally spaced from the conductive elements. Die assemblies comprising the semiconductor structure, methods of forming the semiconductor structure, and methods of forming the die assemblies are also disclosed.

公开(公告)号：US20150140817A1

公开(公告)日：2015-05-21

申请号：US14607945

申请日：2015-01-28

Applicant: Micron Technology, Inc.

Inventor： Ross S. Dando

IPC: H01L21/306

CPC classification number: H01L21/30604 ,  C09K13/00 ,  H01L21/67075 ,  H01L21/6708 ,  H01L21/67086

Abstract: A method for removing material from surfaces of at least a portion of at least one recess or at least one aperture extending into a surface of a substrate includes pressurizing fluid so as to cause the fluid to flow into the at least one recess or the at least one aperture. The fluid may be pressurized by generating a pressure differential across the substrate, which causes the fluid to flow into or through the at least one aperture or recess. Apparatus for pressurizing fluid so as to cause it to flow into or through recesses or apertures in a substrate are also disclosed.

Abstract translation: 从至少一个凹部的至少一部分的至少一部分的表面去除材料的方法或延伸到衬底的表面中的至少一个孔的方法包括加压流体，以使流体流入至少一个凹部或至少 一个孔。 流体可以通过在衬底上产生压差来加压，这导致流体流入或穿过至少一个孔或凹槽。 还公开了用于加压流体以使其流入或穿过基底中的凹部或孔的装置。