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公开(公告)号：US20240021262A1
公开(公告)日：2024-01-18
申请号：US18137388
申请日：2023-04-20
Applicant: Micron Technology, Inc.
Inventor： Takuya Tamano , Yoshinori Fujiwara , Daniel S. Miller
CPC classification number: G11C29/46 , G11C29/4401
Abstract: Methods, apparatuses, and systems related to adjustment of circuit tests are described. A memory device may include a self-test circuit that is configured to selectively suspend collection and/or processing of test results for one or more portions of the self-test.
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公开(公告)号：US20230360718A1
公开(公告)日：2023-11-09
申请号：US17735528
申请日：2022-05-03
Applicant: Micron Technology, Inc.
Inventor： Takuya Tamano , Yoshinori Fujiwara
CPC classification number: G11C29/4401 , G11C29/12
Abstract: Methods, systems, and devices for self-repair verification are described. A memory system may receive, at a memory device, a command to initiate a repair operation. The memory system may perform the repair operation by replacing a first row of memory cells of the memory device with a second row of memory cells of the memory device. The memory system may write first data to the second row of memory cells, and read second data from the second row of memory cells, based on a stored indication associated with the replacement of rows. The memory device may output an error flag with a first value based at least in part on reading the second data, and the first value of the error flag may indicate that the repair operation was successfully performed based at least in part on the second data matching the first data.
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Patent Agency Ranking
公开(公告)号：US20240071560A1
公开(公告)日：2024-02-29
申请号：US17822032
申请日：2022-08-24
Applicant: Micron Technology, Inc.
Inventor： Yoshinori Fujiwara , Takuya Tamano , Jason M. Johnson , Kevin G. Werhane , Daniel S. Miller
CPC classification number: G11C29/789 , G11C29/4401 , G11C29/46
Abstract: An electronic device includes multiple memory elements including multiple redundant memory elements. The electronic device also includes repair circuitry configured to remap data to the multiple memory elements when a failure occurs. The repair circuitry includes multiple fuse latches configured to implement the remapping. The repair circuitry also includes latch testing circuitry configured to test functionality of the multiple fuse latches. The latch testing circuitry includes selection circuitry configured to enable selection of a first set of fuse latches of the multiple fuse latches for a test separate from a second set of fuse latches of the multiple fuse latches that are unselected by the selection circuitry.
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公开(公告)号：US11791011B1
公开(公告)日：2023-10-17
申请号：US17735528
申请日：2022-05-03
Applicant: Micron Technology, Inc.
Inventor： Takuya Tamano , Yoshinori Fujiwara
CPC classification number: G11C29/4401 , G11C29/12
Abstract: Methods, systems, and devices for self-repair verification are described. A memory system may receive, at a memory device, a command to initiate a repair operation. The memory system may perform the repair operation by replacing a first row of memory cells of the memory device with a second row of memory cells of the memory device. The memory system may write first data to the second row of memory cells, and read second data from the second row of memory cells, based on a stored indication associated with the replacement of rows. The memory device may output an error flag with a first value based at least in part on reading the second data, and the first value of the error flag may indicate that the repair operation was successfully performed based at least in part on the second data matching the first data.
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公开(公告)号：US12100476B2
公开(公告)日：2024-09-24
申请号：US17942944
申请日：2022-09-12
Applicant: Micron Technology, Inc.
Inventor： Kari Crane , Kevin G. Werhane , Yoshinori Fujiwara , Jason M. Johnson , Takuya Tamano , Daniel S. Miller
CPC classification number: G11C7/24 , G11C7/1039 , G11C7/1063 , G11C17/16
Abstract: An apparatus includes a TM control circuit that is configured to receive address information corresponding to a TM function and compare the address information with an authorized TM list stored in a memory of the apparatus to determine if there is a match. If there is a match, a latch load signal pulse is output. A TM latch circuit programs one or more latches based on the address information and based on the latch load signal pulse. The TM latch circuit decodes information in the one or more latches and, based on the decoded information, outputs a test mode signal to turn on test mode operations in circuits associated with the TM function. The apparatus includes a plurality of TM functions for testing various features of the apparatus and the authorized TM list identifies which of the plurality of TM functions has been authorized for customer use.
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公开(公告)号：US12100467B2
公开(公告)日：2024-09-24
申请号：US17822032
申请日：2022-08-24
Applicant: Micron Technology, Inc.
Inventor： Yoshinori Fujiwara , Takuya Tamano , Jason M. Johnson , Kevin G. Werhane , Daniel S. Miller
CPC classification number: G11C29/789 , G11C29/027 , G11C29/24 , G11C29/4401 , G11C29/46
Abstract: An electronic device includes multiple memory elements including multiple redundant memory elements. The electronic device also includes repair circuitry configured to remap data to the multiple memory elements when a failure occurs. The repair circuitry includes multiple fuse latches configured to implement the remapping. The repair circuitry also includes latch testing circuitry configured to test functionality of the multiple fuse latches. The latch testing circuitry includes selection circuitry configured to enable selection of a first set of fuse latches of the multiple fuse latches for a test separate from a second set of fuse latches of the multiple fuse latches that are unselected by the selection circuitry.
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公开(公告)号：US20240087625A1
公开(公告)日：2024-03-14
申请号：US17942944
申请日：2022-09-12
Applicant: Micron Technology, Inc.
Inventor： Kari Crane , Kevin G. Werhane , Yoshinori Fujiwara , Jason M. Johnson , Takuya Tamano , Daniel S. Miller
CPC classification number: G11C7/24 , G11C7/1039 , G11C7/1063 , G11C17/16
Abstract: An apparatus includes a TM control circuit that is configured to receive address information corresponding to a TM function and compare the address information with an authorized TM list stored in a memory of the apparatus to determine if there is a match. If there is a match, a latch load signal pulse is output. A TM latch circuit programs one or more latches based on the address information and based on the latch load signal pulse. The TM latch circuit decodes information in the one or more latches and, based on the decoded information, outputs a test mode signal to turn on test mode operations in circuits associated with the TM function. The apparatus includes a plurality of TM functions for testing various features of the apparatus and the authorized TM list identifies which of the plurality of TM functions has been authorized for customer use.
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