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公开(公告)号：US12100476B2
公开(公告)日：2024-09-24
申请号：US17942944
申请日：2022-09-12
Applicant: Micron Technology, Inc.
Inventor： Kari Crane , Kevin G. Werhane , Yoshinori Fujiwara , Jason M. Johnson , Takuya Tamano , Daniel S. Miller
CPC classification number: G11C7/24 , G11C7/1039 , G11C7/1063 , G11C17/16
Abstract: An apparatus includes a TM control circuit that is configured to receive address information corresponding to a TM function and compare the address information with an authorized TM list stored in a memory of the apparatus to determine if there is a match. If there is a match, a latch load signal pulse is output. A TM latch circuit programs one or more latches based on the address information and based on the latch load signal pulse. The TM latch circuit decodes information in the one or more latches and, based on the decoded information, outputs a test mode signal to turn on test mode operations in circuits associated with the TM function. The apparatus includes a plurality of TM functions for testing various features of the apparatus and the authorized TM list identifies which of the plurality of TM functions has been authorized for customer use.
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公开(公告)号：US12100467B2
公开(公告)日：2024-09-24
申请号：US17822032
申请日：2022-08-24
Applicant: Micron Technology, Inc.
Inventor： Yoshinori Fujiwara , Takuya Tamano , Jason M. Johnson , Kevin G. Werhane , Daniel S. Miller
CPC classification number: G11C29/789 , G11C29/027 , G11C29/24 , G11C29/4401 , G11C29/46
Abstract: An electronic device includes multiple memory elements including multiple redundant memory elements. The electronic device also includes repair circuitry configured to remap data to the multiple memory elements when a failure occurs. The repair circuitry includes multiple fuse latches configured to implement the remapping. The repair circuitry also includes latch testing circuitry configured to test functionality of the multiple fuse latches. The latch testing circuitry includes selection circuitry configured to enable selection of a first set of fuse latches of the multiple fuse latches for a test separate from a second set of fuse latches of the multiple fuse latches that are unselected by the selection circuitry.
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公开(公告)号：US20240087625A1
公开(公告)日：2024-03-14
申请号：US17942944
申请日：2022-09-12
Applicant: Micron Technology, Inc.
Inventor： Kari Crane , Kevin G. Werhane , Yoshinori Fujiwara , Jason M. Johnson , Takuya Tamano , Daniel S. Miller
CPC classification number: G11C7/24 , G11C7/1039 , G11C7/1063 , G11C17/16
Abstract: An apparatus includes a TM control circuit that is configured to receive address information corresponding to a TM function and compare the address information with an authorized TM list stored in a memory of the apparatus to determine if there is a match. If there is a match, a latch load signal pulse is output. A TM latch circuit programs one or more latches based on the address information and based on the latch load signal pulse. The TM latch circuit decodes information in the one or more latches and, based on the decoded information, outputs a test mode signal to turn on test mode operations in circuits associated with the TM function. The apparatus includes a plurality of TM functions for testing various features of the apparatus and the authorized TM list identifies which of the plurality of TM functions has been authorized for customer use.
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公开(公告)号：US11742044B2
公开(公告)日：2023-08-29
申请号：US17411206
申请日：2021-08-25
Applicant: Micron Technology, Inc.
Inventor： Yoshinori Fujiwara , Daniel S. Miller
CPC classification number: G11C29/36 , G11C29/12015 , G11C29/4401 , G11C29/46 , G11C2029/3602
Abstract: An apparatus with a memory array having a plurality of memory cells. The apparatus also including a memory built-in self-test circuit to test the memory array. The memory built-in self-test circuit includes one or more processing devices to write a data pattern to one or more memory cells to be tested in the memory array, pause for a time period corresponding to a predetermined pause time setting, and read the written data pattern from the one or more memory cells after the time period has elapsed. The predetermined pause time setting is automatically adjusted based on memory device conditions, which can include the temperature of the apparatus.
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公开(公告)号：US11675589B2
公开(公告)日：2023-06-13
申请号：US17464650
申请日：2021-09-01
Applicant: Micron Technology, Inc.
Inventor： Kevin G. Werhane , Daniel S. Miller
CPC classification number: G06F9/30116 , G06F13/4282
Abstract: Serial interfaces with shadow registers, and associated systems, devices, and methods are described herein. In one embodiment, a serial interface is an IEEE 1500 interface, such as of an interface die of a high bandwidth memory (HBM) device. The IEEE 1500 interface includes (a) a primary wrapper data register (WDR) configured to store first information received in a first wrapper serial input (WSI) signal, (b) a shadow WDR configured to store second information received in a second WSI signal, and (c) a multiplexer. The multiplexer is configured to (i) receive the first information from the primary WDR, (ii) receive the second information from the shadow WDR, and (iii) output the first information or the second information based at least in part on a control signal input into the multiplexer.
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Patent Agency Ranking
公开(公告)号：US11645134B2
公开(公告)日：2023-05-09
申请号：US16545721
申请日：2019-08-20
Applicant: Micron Technology, Inc.
Inventor： Daniel S. Miller , Kevin G. Werhane , Yoshinori Fujiwara , Christopher G. Wieduwilt , Jason M. Johnson , Minoru Someya
CPC classification number: G06F11/0751 , G06F11/0727 , G11C17/16 , H03K19/21
Abstract: An example fuse error detection circuit configured to receive a first data set from a fuse array during a first fuse data broadcast and to encode the first data set to provide first signature data. The fuse error detection circuit is further configured to receive a second data set from the fuse array during a second fuse data broadcast and to encode the second data set to provide second signature data. The fuse error detection circuit is further configured to compare the first signature data and the second signature data and to provide a match indication having a value based on the comparison between the first signature data and the second signature data.
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公开(公告)号：US20200211635A1
公开(公告)日：2020-07-02
申请号：US16812854
申请日：2020-03-09
Applicant: Micron Technology, Inc.
IPC: G11C11/406 , G11C5/14 , G11C11/4091 , G11C8/10 , G11C11/4074
Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for timing refresh operations in a memory device. An apparatus may include an oscillator that provides a periodic signal to one or more refresh timer circuits. Each of the refresh timer circuits is associated with a respective memory bank in the memory device. The refresh timer may include a counter block and a control logic block. The control logic block may gate the periodic signal to the counter block. The counter block may count the row active signal time and the row precharge time. The counter signals may be used by the control logic block to output a number of pumps of a refresh operation.
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公开(公告)号：US20230420030A1
公开(公告)日：2023-12-28
申请号：US17846967
申请日：2022-06-22
Applicant: Micron Technology, Inc.
Inventor： Yoshinori Fujiwara , Kevin G. Werhane , Jason M. Johnson , Daniel S. Miller
IPC: G11C11/4076 , H03K5/133 , G11C29/54
CPC classification number: G11C11/4076 , H03K5/133 , G11C29/54
Abstract: A delay circuit is coupled to a memory device. At least a portion of the delay circuit is disposed in one or more memory banks on one or more memory chips of the memory device. The delay circuit is configured to calibrate an asynchronous signal received at each of the one or more memory banks so that the calibrated asynchronous signal has a common timing relationship with a respective internal command signal received at the corresponding memory bank for all of the one or more memory banks on the memory device. The calibrated asynchronous signals are used in various internal test operations to improve testing accuracy.
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公开(公告)号：US10930327B1
公开(公告)日：2021-02-23
申请号：US16773824
申请日：2020-01-27
Applicant: Micron Technology, Inc.
Inventor： Dave Jefferson , C. Omar Benitez , Yoshinori Fujiwara , Christopher S. Wieduwilt , Vivek Kotti , Dennis G. Montierth , Joshua E. Alzheimer , Daniel S. Miller , Kevin G. Werhane , Jason M. Johnson
Abstract: Methods, systems, and devices for memory read masking are described. In some cases, a portion of a memory device, such as a portion of a memory array, may be disabled. During a testing operation, a command for accessing one or more memory cells of the disabled portion may be received, and the associated memory cells may be attempted to be accessed. Based on attempting to access the disabled memory cells, a logic state of the disabled cells may be masked. Outputting the masked value may indicate (e.g., to a testing device) that the disabled cells pass the test (e.g., that the memory cells are valid), which may allow for the enabled memory cells and the disabled memory cells of the memory device to be tested using a single test mode.
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公开(公告)号：US20240127901A1
公开(公告)日：2024-04-18
申请号：US17968717
申请日：2022-10-18
Applicant: Micron Technology, Inc.
Inventor： Daniel S. Miller , Yoshinori Fujiwara
CPC classification number: G11C29/46 , G11C29/12015 , G11C29/44 , G11C2029/4402
Abstract: Methods, apparatuses, and systems related to masking of self-test results are described. A memory device may include a self-test circuit that is configured to selectively suspend collection of test results from one or more portions of a self-test when a temperature of the memory device exceeds a temperature threshold.
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