公开(公告)号：US11921647B2

公开(公告)日：2024-03-05

申请号：US18092748

申请日：2023-01-03

Applicant: Micron Technology, Inc.

Inventor： Keith A Benjamin ,  Thomas Dougherty

IPC: G06F13/12 ,  G05F1/66 ,  G06F1/32 ,  G06F1/3203

CPC classification number: G06F13/126 ,  G05F1/66 ,  G06F1/3203

Abstract: A system can include a plurality of sequencers each configured to provide a number of sequenced output signals responsive to assertion of a respective sequencer enable signal provided thereto. The system can include chaining circuitry coupled to the plurality of sequencers. The chaining circuitry can comprise logic to: responsive to assertion of a primary enable signal received thereby, assert respective sequencer enable signals provided to the plurality of sequencers in accordance with a first sequence; and responsive to deassertion of the primary enable signal, assert the respective sequencer enable signals provided to the plurality of sequencers in accordance with a second sequence.

公开(公告)号：US11868280B2

公开(公告)日：2024-01-09

申请号：US18092748

申请日：2023-01-03

Applicant: Micron Technology, Inc.

Inventor： Keith A Benjamin ,  Thomas Dougherty

IPC: G06F13/12 ,  G06F1/32 ,  G05F1/66 ,  G06F1/3203

CPC classification number: G06F13/126 ,  G05F1/66 ,  G06F1/3203

Abstract: A system can include a plurality of sequencers each configured to provide a number of sequenced output signals responsive to assertion of a respective sequencer enable signal provided thereto. The system can include chaining circuitry coupled to the plurality of sequencers. The chaining circuitry can comprise logic to: responsive to assertion of a primary enable signal received thereby, assert respective sequencer enable signals provided to the plurality of sequencers in accordance with a first sequence; and responsive to deassertion of the primary enable signal, assert the respective sequencer enable signals provided to the plurality of sequencers in accordance with a second sequence.

公开(公告)号：US20230145999A1

公开(公告)日：2023-05-11

申请号：US18092748

申请日：2023-01-03

Applicant: Micron Technology, Inc.

Inventor： Keith A. Benjamin ,  Thomas Dougherty

IPC: G06F13/12 ,  G05F1/66 ,  G06F1/3203

CPC classification number: G06F13/126 ,  G05F1/66 ,  G06F1/3203

Abstract: A system can include a plurality of sequencers each configured to provide a number of sequenced output signals responsive to assertion of a respective sequencer enable signal provided thereto. The system can include chaining circuitry coupled to the plurality of sequencers. The chaining circuitry can comprise logic to: responsive to assertion of a primary enable signal received thereby, assert respective sequencer enable signals provided to the plurality of sequencers in accordance with a first sequence; and responsive to deassertion of the primary enable signal, assert the respective sequencer enable signals provided to the plurality of sequencers in accordance with a second sequence.

公开(公告)号：US11353942B2

公开(公告)日：2022-06-07

申请号：US17126651

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Keith A. Benjamin ,  Thomas Dougherty

IPC: G11C8/18 ,  G06F1/3203 ,  G05B15/02 ,  G11C16/10

Abstract: A system can comprise a memory device and sequencing circuitry configured to provide enable signals to a number of voltage regulators in association with providing sequenced power signals to the memory device. The system can include voltage threshold detection circuitry configured to: detect primary supply voltage events; and responsive to detecting a primary supply voltage event, deassert a timer enable signal provided to timing circuitry. The timing circuitry is configured to, responsive to the deassertion of the timer enable signal: deassert a primary enable signal provided to the sequencing circuitry; and maintain the primary enable signal in a deasserted state for a particular amount of time prior to reasserting the primary enable signal.

公开(公告)号：US11544203B2

公开(公告)日：2023-01-03

申请号：US16816615

申请日：2020-03-12

Applicant: Micron Technology, Inc.

Inventor： Keith A. Benjamin ,  Thomas Dougherty

IPC: G06F13/12 ,  G06F1/32 ,  G05F1/66 ,  G06F1/3203

Abstract: A system can include a plurality of sequencers each configured to provide a number of sequenced output signals responsive to assertion of a respective sequencer enable signal provided thereto. The system can include chaining circuitry coupled to the plurality of sequencers. The chaining circuitry can comprise logic to: responsive to assertion of a primary enable signal received thereby, assert respective sequencer enable signals provided to the plurality of sequencers in accordance with a first sequence; and responsive to deassertion of the primary enable signal, assert the respective sequencer enable signals provided to the plurality of sequencers in accordance with a second sequence.

公开(公告)号：US20210200693A1

公开(公告)日：2021-07-01

申请号：US16816615

申请日：2020-03-12

Applicant: Micron Technology, Inc.

Inventor： Keith A. Benjamin ,  Thomas Dougherty

IPC: G06F13/12 ,  G06F1/3203 ,  G05F1/66

Abstract: A system can include a plurality of sequencers each configured to provide a number of sequenced output signals responsive to assertion of a respective sequencer enable signal provided thereto. The system can include chaining circuitry coupled to the plurality of sequencers. The chaining circuitry can comprise logic to: responsive to assertion of a primary enable signal received thereby, assert respective sequencer enable signals provided to the plurality of sequencers in accordance with a first sequence; and responsive to deassertion of the primary enable signal, assert the respective sequencer enable signals provided to the plurality of sequencers in accordance with a second sequence.

公开(公告)号：US20210200292A1

公开(公告)日：2021-07-01

申请号：US17126651

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Keith A. Benjamin ,  Thomas Dougherty

IPC: G06F1/3203 ,  G05B15/02 ,  G11C16/10

Abstract: A system can comprise a memory device and sequencing circuitry configured to provide enable signals to a number of voltage regulators in association with providing sequenced power signals to the memory device. The system can include voltage threshold detection circuitry configured to: detect primary supply voltage events; and responsive to detecting a primary supply voltage event, deassert a timer enable signal provided to timing circuitry. The timing circuitry is configured to, responsive to the deassertion of the timer enable signal: deassert a primary enable signal provided to the sequencing circuitry; and maintain the primary enable signal in a deasserted state for a particular amount of time prior to reasserting the primary enable signal.