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公开(公告)号：US20220365714A1
公开(公告)日：2022-11-17
申请号：US17316942
申请日：2021-05-11
Applicant: Micron Technology, Inc.
Inventor： Keith A. Benjamin
Abstract: An example embodiment includes an n-bit parallel pseudo-random binary sequence (PRBS) generator coupled to channelization circuitry to control the channelization circuitry to select from among a single channel n-bit output pattern from the PRBS generator and a number of multiple channel output patterns from the PRBS generator. The number of multiple channel output patterns can correspond to respective sub-patterns of the single channel n-bit output pattern.
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公开(公告)号：US20240012616A1
公开(公告)日：2024-01-11
申请号：US17811846
申请日：2022-07-11
Applicant: Micron Technology, Inc.
Inventor： Keith A. Benjamin
IPC: G06F7/544
CPC classification number: G06F7/5443 , G06F2207/581
Abstract: Methods, systems, and devices for a programmable finite field generator for memory are described. In some cases, a system (e.g., a memory system, a host system) may store coefficient values indicating Galois Field multipliers in an array of configuration registers associated with a finite field generator. To update a set of values stored in a set of registers associated with the finite field generator, the system may perform a set of Galois Field multiplication operations according to Galois Field multipliers indicated by the coefficient values stored in the array of configuration registers. The system may perform at least one Galois Field summation operation on one or more of the multiplied values to generate an updated value. Then, the system may store the updated value in a first register from the set of registers, and shift the set of values along the remaining set of registers.
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公开(公告)号：US20210181978A1
公开(公告)日：2021-06-17
申请号：US16716848
申请日：2019-12-17
Applicant: Micron Technology, Inc.
Inventor： Gary R. Van Sickle , Jacob Sloat , Keith A. Benjamin
Abstract: A method includes receiving, by a memory sub-system and responsive to initiation of an operation, a bit string containing information corresponding to initiation of the operation. The operation can be initiated by circuitry external to the memory sub-system and the bit string can be generated by circuitry external to the memory sub-system. The method can further include storing, responsive to receipt of the bit string, the bit string in a first portion of a plurality of storage locations resident on the memory sub-system.
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公开(公告)号：US20230145999A1
公开(公告)日：2023-05-11
申请号：US18092748
申请日：2023-01-03
Applicant: Micron Technology, Inc.
Inventor： Keith A. Benjamin , Thomas Dougherty
IPC: G06F13/12 , G05F1/66 , G06F1/3203
CPC classification number: G06F13/126 , G05F1/66 , G06F1/3203
Abstract: A system can include a plurality of sequencers each configured to provide a number of sequenced output signals responsive to assertion of a respective sequencer enable signal provided thereto. The system can include chaining circuitry coupled to the plurality of sequencers. The chaining circuitry can comprise logic to: responsive to assertion of a primary enable signal received thereby, assert respective sequencer enable signals provided to the plurality of sequencers in accordance with a first sequence; and responsive to deassertion of the primary enable signal, assert the respective sequencer enable signals provided to the plurality of sequencers in accordance with a second sequence.
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公开(公告)号：US11353942B2
公开(公告)日：2022-06-07
申请号：US17126651
申请日：2020-12-18
Applicant: Micron Technology, Inc.
Inventor： Keith A. Benjamin , Thomas Dougherty
IPC: G11C8/18 , G06F1/3203 , G05B15/02 , G11C16/10
Abstract: A system can comprise a memory device and sequencing circuitry configured to provide enable signals to a number of voltage regulators in association with providing sequenced power signals to the memory device. The system can include voltage threshold detection circuitry configured to: detect primary supply voltage events; and responsive to detecting a primary supply voltage event, deassert a timer enable signal provided to timing circuitry. The timing circuitry is configured to, responsive to the deassertion of the timer enable signal: deassert a primary enable signal provided to the sequencing circuitry; and maintain the primary enable signal in a deasserted state for a particular amount of time prior to reasserting the primary enable signal.
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Patent Agency Ranking
公开(公告)号：US20210210155A1
公开(公告)日：2021-07-08
申请号：US17211133
申请日：2021-03-24
Applicant: Micron Technology, Inc.
Inventor： Nathan A. Eckel , Keith A. Benjamin
Abstract: A method includes requesting, by a component of a memory sub-system controller, control of a data path associated with a memory device coupleable to the controller. The method can include generating, by the component, data corresponding to an operation to test the memory device and causing, by the component, the data to be injected to the data path such that the data is written to the memory device. The method can further include reading, by the component, the data written to the memory device and determining, by the component, whether the data read by the component from the memory device matches the data written to the memory device.
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公开(公告)号：US10984881B1
公开(公告)日：2021-04-20
申请号：US16713108
申请日：2019-12-13
Applicant: Micron Technology, Inc.
Inventor： Nathan A. Eckel , Keith A. Benjamin
Abstract: A method includes requesting, by a component of a memory sub-system controller, control of a data path associated with a memory device coupleable to the controller. The method can include generating, by the component, data corresponding to an operation to test the memory device and causing, by the component, the data to be injected to the data path such that the data is written to the memory device. The method can further include reading, by the component, the data written to the memory device and determining, by the component, whether the data read by the component from the memory device matches the data written to the memory device.
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公开(公告)号：US12019912B2
公开(公告)日：2024-06-25
申请号：US17316942
申请日：2021-05-11
Applicant: Micron Technology, Inc.
Inventor： Keith A. Benjamin
IPC: G06F3/06 , G06F7/58 , G11C11/409 , H03K3/84
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679 , G06F7/584 , H03K3/84 , G11C11/409
Abstract: An example embodiment includes an n-bit parallel pseudo-random binary sequence (PRBS) generator coupled to channelization circuitry to control the channelization circuitry to select from among a single channel n-bit output pattern from the PRBS generator and a number of multiple channel output patterns from the PRBS generator. The number of multiple channel output patterns can correspond to respective sub-patterns of the single channel n-bit output pattern.
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公开(公告)号：US11544203B2
公开(公告)日：2023-01-03
申请号：US16816615
申请日：2020-03-12
Applicant: Micron Technology, Inc.
Inventor： Keith A. Benjamin , Thomas Dougherty
IPC: G06F13/12 , G06F1/32 , G05F1/66 , G06F1/3203
Abstract: A system can include a plurality of sequencers each configured to provide a number of sequenced output signals responsive to assertion of a respective sequencer enable signal provided thereto. The system can include chaining circuitry coupled to the plurality of sequencers. The chaining circuitry can comprise logic to: responsive to assertion of a primary enable signal received thereby, assert respective sequencer enable signals provided to the plurality of sequencers in accordance with a first sequence; and responsive to deassertion of the primary enable signal, assert the respective sequencer enable signals provided to the plurality of sequencers in accordance with a second sequence.
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公开(公告)号：US11514995B2
公开(公告)日：2022-11-29
申请号：US17211133
申请日：2021-03-24
Applicant: Micron Technology, Inc.
Inventor： Nathan A. Eckel , Keith A. Benjamin
Abstract: A method includes requesting, by a component of a memory sub-system controller, control of a data path associated with a memory device coupleable to the controller. The method can include generating, by the component, data corresponding to an operation to test the memory device and causing, by the component, the data to be injected to the data path such that the data is written to the memory device. The method can further include reading, by the component, the data written to the memory device and determining, by the component, whether the data read by the component from the memory device matches the data written to the memory device.
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