公开(公告)号：US10347303B2

公开(公告)日：2019-07-09

申请号：US15666320

申请日：2017-08-01

Applicant: Micron Technology, Inc.

Inventor： Timothy Mowry Hollis

IPC: G11C5/14 ,  H02M3/156 ,  G11C11/4074 ,  H02M1/00

Abstract: Various embodiments, disclosed herein, include apparatus and methods to provide separate regulated voltages to an electronic device. Multiple voltage regulators can be provided with phase alignment circuitry coupled to the multiple voltage regulators. The multiple voltage regulators can be structured with each voltage regulator having an output separate from the output of the other voltage regulators. The phase alignment circuitry can provide for relative phases among voltage regulator ripples at the output pins of the multiple voltage regulators to be maintained at a certain relationship. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20190138388A1

公开(公告)日：2019-05-09

申请号：US16183136

申请日：2018-11-07

Applicant: Micron Technology, Inc.

Inventor： Timothy Mowry Hollis

IPC: G06F11/10

Abstract: Implementations of Data Bus Inversion (DBI) techniques within a memory system are disclosed. In one embodiment, a set of random access memory (RAM) integrated circuits (ICs) is separated from a logic system by a bus. The logic system can contain many of the logic functions traditionally performed on conventional RAM ICs, and accordingly the RAM ICs can be modified to not include such logic functions. The logic system, which can be a logic integrated circuit intervening between the modified RAM IC's and a traditional memory controller, additionally contains DBI encoding and decoding circuitry. In such a system, data is DBI encoded and at least one DBI bit issued when writing to the modified RAM ICs. The RAM ICs in turn store the DBI bit(s) with the encoded data. When the encoded data is read from the modified RAM ICs, it is transmitted across the bus in its encoded state along with the DBI bit(s). The logic integrated circuit then decodes the data using the DBI bit(s) to return it to its original state.

公开(公告)号：US20200341838A1

公开(公告)日：2020-10-29

申请号：US16871540

申请日：2020-05-11

Applicant: Micron Technology, Inc.

Inventor： Timothy Mowry Hollis

IPC: G06F11/10

Abstract: Implementations of Data Bus Inversion (DBI) techniques within a memory system are disclosed. In one embodiment, a set of random access memory (RAM) integrated circuits (ICs) is separated from a logic system by a bus. The logic system can contain many of the logic functions traditionally performed on conventional RAM ICs, and accordingly the RAM ICs can be modified to not include such logic functions. The logic system, which can be a logic integrated circuit intervening between the modified RAM ICs and a traditional memory controller, additionally contains DBI encoding and decoding circuitry. In such a system, data is DBI encoded and at least one DBI bit issued when writing to the modified RAM ICs. The RAM ICs in turn store the DBI bit(s) with the encoded data. When the encoded data is read from the modified RAM ICs, it is transmitted across the bus in its encoded state along with the DBI bit(s). The logic integrated circuit then decodes the data using the DBI bit(s) to return it to its original state.

公开(公告)号：US20190287575A1

公开(公告)日：2019-09-19

申请号：US16428527

申请日：2019-05-31

Applicant: Micron Technology, Inc.

Inventor： Timothy Mowry Hollis

IPC: G11C5/14 ,  H02M3/156 ,  H02M3/158 ,  H02M1/15 ,  G11C11/4074

Abstract: Various embodiments, disclosed herein, include apparatus and methods to provide separate regulated voltages to an electronic device. Multiple voltage regulators can be provided with phase alignment circuitry coupled to the multiple voltage regulators. The multiple voltage regulators can be structured with each voltage regulator having an output separate from the output of the other voltage regulators. The phase alignment circuitry can provide for relative phases among voltage regulator ripples at the output pins of the multiple voltage regulators to be maintained at a certain relationship. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US10164805B1

公开(公告)日：2018-12-25

申请号：US15689721

申请日：2017-08-29

Applicant: Micron Technology, Inc.

Inventor： Timothy Mowry Hollis

IPC: H04L25/03

Abstract: Various embodiments, disclosed herein, can include apparatus and methods to characterize taps of a decision feedback equalizer of a data receiver. In characterizing the taps of the decision feedback equalizer of the data receiver, a signal can be transmitted to the data receiver and the received data can be iteratively sampled at an output of the decision feedback equalizer. The sampling can include stepping a sample time relative to arrival of the received data and stepping a reference voltage level to which the received data is compared. Values of the sampled data can be compared with known correct values and such measurements can be used to characterize the taps. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20230126998A1

公开(公告)日：2023-04-27

申请号：US17982047

申请日：2022-11-07

Applicant: Micron Technology, Inc.

Inventor： Timothy Mowry Hollis

IPC: G06F11/20 ,  G06F13/40 ,  G06F11/30 ,  G06F11/10 ,  G06F11/22

Abstract: Implementations of encoding techniques are disclosed. The encoding technique, such as a Data bus Inversion (DBD technique, is implementable in a vertically-stacked memory module, but is not limited thereto. The module can be a plurality of memory integrated circuits which are vertically stacked, and which communicate via a bus formed in one embodiment of channels comprising Through-Wafer Interconnects (TWIs), but again is not limited thereto. One such module includes spare channels that are normally used to reroute a data signal on the bus away from faulty data channels. In one disclosed technique, the status of a spare channel or channels is queried, and if one or more are unused, they can be used to carry a DBI bit, thus allowing at least a portion of the bus to be assessed in accordance with a DBI algorithm. Depending on the location and number of spare channels needed for rerouting, DBI can be apportioned across the bus in various manners. Implementations can also be used with other encoding techniques not comprising DBL

公开(公告)号：US10698776B2

公开(公告)日：2020-06-30

申请号：US15954149

申请日：2018-04-16

Applicant: Micron Technology, Inc.

Inventor： Timothy Mowry Hollis

IPC: G06F11/20 ,  G06F13/40 ,  G06F11/30 ,  G06F11/10 ,  G06F11/22 ,  G06F13/28

Abstract: Implementations of encoding techniques are disclosed. The encoding technique, such as a Data bus Inversion (DBI) technique, is implementable in a vertically-stacked memory module, but is not limited thereto. The module can be a plurality of memory integrated circuits which are vertically stacked, and which communicate via a bus formed in one embodiment of channels comprising Through-Wafer Interconnects (TWIs), but again is not limited thereto. One such module includes spare channels that are normally used to reroute a data signal on the bus away from faulty data channels. In one disclosed technique, the status of a spare channel or channels is queried, and if one or more are unused, they can be used to carry a DBI bit, thus allowing at least a portion of the bus to be assessed in accordance with a DBI algorithm. Depending on the location and number of spare channels needed for rerouting, DBI can be apportioned across the bus in various manners. Implementations can also be used with other encoding techniques not comprising DBI.

公开(公告)号：US10523473B2

公开(公告)日：2019-12-31

申请号：US16201671

申请日：2018-11-27

Applicant: Micron Technology, Inc.

Inventor： Timothy Mowry Hollis

IPC: H04B3/30 ,  H04L25/03

Abstract: Various embodiments, disclosed herein, can include apparatus and methods to characterize taps of a decision feedback equalizer of a data receiver. In characterizing the taps of the decision feedback equalizer of the data receiver, a signal can be transmitted to the data receiver and the received data can be iteratively sampled at an output of the decision feedback equalizer. The sampling can include stepping a sample time relative to arrival of the received data and stepping a reference voltage level to which the received data is compared. Values of the sampled data can be compared with known correct values and such measurements can be used to characterize the taps. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US10339075B2

公开(公告)日：2019-07-02

申请号：US15693027

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Roy E. Greeff ,  George Pax ,  Timothy Mowry Hollis

IPC: G06F12/00 ,  G06F13/16 ,  G06F1/10 ,  G06F13/40 ,  G06F13/42

Abstract: A computing system including multiple integrated circuit memory devices is described. One or more command and address buses are connected to the memory devices to transmit command and address signals to each memory device. Multiple clock lines are connected to the multiple memory devices in a tree structure to transmit multiple clock signals to these memory devices. The tree structure allows each distributed clock signal to be individually trained such that the multiple clock signals provide each memory device with a clock signal that is temporally aligned with the command and address signals as received by that memory device.

公开(公告)号：US11664057B2

公开(公告)日：2023-05-30

申请号：US17374601

申请日：2021-07-13

Applicant: Micron Technology, Inc.

Inventor： Aparna U. Limaye ,  Timothy Mowry Hollis

IPC: G11C7/10 ,  G11C5/06

CPC classification number: G11C7/1012 ,  G11C5/06 ,  G11C7/109 ,  G11C7/1039 ,  G11C7/1063

Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. Example memory devices, systems and methods include a multiplexer circuit to further facilitate use of slower, and wider bandwidth memory devices. Devices and methods described may be configured to substantially match the capacity of a narrower, higher speed host interface.