公开(公告)号：US12114474B2

公开(公告)日：2024-10-08

申请号：US17877628

申请日：2022-07-29

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: G11C11/24 ,  G11C11/4091 ,  G11C11/4094 ,  H01L29/78 ,  H10B12/00

CPC classification number: H10B12/00 ,  G11C11/4091 ,  G11C11/4094 ,  H01L29/78 ,  H01L29/7827 ,  H10B12/50

Abstract: Some embodiments include an integrated assembly having a primary access transistor. The primary access transistor has a first source/drain region and a second source/drain region. The first and second source/drain regions are coupled to one another when the primary access transistor is in an ON mode, and are not coupled to one another when the primary access transistor is in an OFF mode. A charge-storage device is coupled with the first source/drain region. A digit line is coupled with the second source/drain region through a secondary access device. The secondary access device has an ON mode and an OFF mode. The digit line is coupled with the charge-storage device only when both the primary access transistor and the secondary access device are in their respective ON modes.

公开(公告)号：US20220367465A1

公开(公告)日：2022-11-17

申请号：US17877628

申请日：2022-07-29

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: H01L27/108 ,  H01L29/78 ,  G11C11/4094 ,  G11C11/4091

Abstract: Some embodiments include an integrated assembly having a primary access transistor. The primary access transistor has a first source/drain region and a second source/drain region. The first and second source/drain regions are coupled to one another when the primary access transistor is in an ON mode, and are not coupled to one another when the primary access transistor is in an OFF mode. A charge-storage device is coupled with the first source/drain region. A digit line is coupled with the second source/drain region through a secondary access device. The secondary access device has an ON mode and an OFF mode. The digit line is coupled with the charge-storage device only when both the primary access transistor and the secondary access device are in their respective ON modes.

公开(公告)号：US20210398582A1

公开(公告)日：2021-12-23

申请号：US17370515

申请日：2021-07-08

Applicant: Micron Technology, Inc.

Inventor： Charles L. Ingalls ,  Scott J. Derner

IPC: G11C11/22

Abstract: Methods, systems, and apparatuses for memory array bit inversion are described. A memory cell (e.g., a ferroelectric memory cell) may be written with a charge associated with a logic state that may be the inverse of the intended logic state of the cell. That is, the actual logic state of one or more memory cells may be inverted, but the intended logic state of the memory cells may remain unchanged. Different sets of transistors may be configured around a sense component of a cell to enable reading and writing of intended and inverted logic states from or to the cell. For instance, a first set of transistors may be used to read the logic state currently stored at a memory cell, while a second set of transistors may be used to read a logic state inverted from the currently stored logic state.

公开(公告)号：US11200937B2

公开(公告)日：2021-12-14

申请号：US16675021

申请日：2019-11-05

Applicant: Micron Technology, Inc.

Inventor： Scott James Derner ,  Christopher John Kawamura ,  Charles L. Ingalls

IPC: G11C11/22

Abstract: Methods, systems, and apparatuses related to a reprogrammable non-volatile latch are described. A latch may include ferroelectric cells, ferroelectric capacitors, a sense component, and other circuitry and components related to ferroelectric memory technology. The ferroelectric latch may be independent from (or exclusive of) a main ferroelectric memory array. The ferroelectric latch may be positioned anywhere in the memory device. In some instances, a ferroelectric latch may be positioned and configured to be dedicated to single piece of circuitry in the memory device.

公开(公告)号：US20210183428A1

公开(公告)日：2021-06-17

申请号：US17171853

申请日：2021-02-09

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: G11C11/408 ,  H01L27/108 ,  G11C11/4097 ,  G11C11/404 ,  G11C11/405 ,  H01L23/528 ,  H01L27/02 ,  H01L49/02 ,  H01L29/78

Abstract: Some embodiments include an integrated memory assembly having a first memory array deck over a second memory array deck. A first series of conductive lines extends across the first memory array deck, and a second series of conductive lines extends across the second memory array deck. A first conductive line of the first series and a first conductive line of the second series are coupled with a first component through a first conductive path. A second conductive line of the first series and a second conductive line of the second series are coupled with a second component through a second conductive path. The first and second conductive lines of the first series extend through first isolation circuitry to the first and second conductive paths, respectively; and the first and second conductive lines of the second series extend through second isolation circuitry to the first and second conductive paths, respectively.

公开(公告)号：US20210090636A1

公开(公告)日：2021-03-25

申请号：US17114404

申请日：2020-12-07

Applicant: Micron Technology, Inc.

Inventor： Christopher J. Kawamura ,  Charles L. Ingalls ,  Tae H. Kim

IPC: G11C11/408 ,  G11C11/4076

Abstract: An apparatus includes a plurality of main word line circuits. Each main word line circuit drives a respective global word line to one of an active state value, an intermediate voltage state, or a pre-charge state. The intermediate voltage state voltage is below the active state voltage and above the pre-charge state voltage. The memory device also includes a plurality of sub-word line drivers. Each sub-word line driver is connected to a corresponding global word line and configured to drive a respective local word line between the corresponding global word line voltage and a low voltage value. The apparatus further includes a plurality of phase drivers. Each phase driver is connected to a predetermined number of sub-word line drivers, where each of the predetermined number of sub-word line drivers connects to a different global word line.

公开(公告)号：US10943642B2

公开(公告)日：2021-03-09

申请号：US16838618

申请日：2020-04-02

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: G11C11/408 ,  H01L27/108 ,  G11C11/4097 ,  G11C11/404 ,  G11C11/405 ,  H01L23/528 ,  H01L27/02 ,  H01L49/02 ,  H01L29/78 ,  G11C11/4091 ,  G11C11/4094

Abstract: Some embodiments include an integrated memory assembly having a first memory array deck over a second memory array deck. A first series of conductive lines extends across the first memory array deck, and a second series of conductive lines extends across the second memory array deck. A first conductive line of the first series and a first conductive line of the second series are coupled with a first component through a first conductive path. A second conductive line of the first series and a second conductive line of the second series are coupled with a second component through a second conductive path. The first and second conductive lines of the first series extend through first isolation circuitry to the first and second conductive paths, respectively; and the first and second conductive lines of the second series extend through second isolation circuitry to the first and second conductive paths, respectively.

公开(公告)号：US20200328220A1

公开(公告)日：2020-10-15

申请号：US16379365

申请日：2019-04-09

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: H01L27/11507 ,  H01L29/78 ,  H01L29/08 ,  H01L23/528 ,  H01L27/108 ,  H01L27/11514

Abstract: Some embodiments include an integrated assembly. The integrated assembly has a first transistor with a horizontally-extending channel region between a first source/drain region and a second source/drain region; has a second transistor with a vertically-extending channel region between a third source/drain region and a fourth source/drain region; and has a capacitor between the first and second transistors. The capacitor has a first electrode, a second electrode, and an insulative material between the first and second electrodes. The first electrode is electrically connected with the first source/drain region, and the second electrode is electrically connected with the third source/drain region. A digit line is electrically connected with the second source/drain region. A conductive structure is electrically connected with the fourth source/drain region.

公开(公告)号：US20200234754A1

公开(公告)日：2020-07-23

申请号：US16838618

申请日：2020-04-02

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: G11C11/408 ,  H01L29/78 ,  H01L49/02 ,  H01L27/108 ,  H01L27/02 ,  H01L23/528 ,  G11C11/405 ,  G11C11/404 ,  G11C11/4097

Abstract: Some embodiments include an integrated memory assembly having a first memory array deck over a second memory array deck. A first series of conductive lines extends across the first memory array deck, and a second series of conductive lines extends across the second memory array deck. A first conductive line of the first series and a first conductive line of the second series are coupled with a first component through a first conductive path. A second conductive line of the first series and a second conductive line of the second series are coupled with a second component through a second conductive path. The first and second conductive lines of the first series extend through first isolation circuitry to the first and second conductive paths, respectively; and the first and second conductive lines of the second series extend through second isolation circuitry to the first and second conductive paths, respectively.

公开(公告)号：US20200082870A1

公开(公告)日：2020-03-12

申请号：US16125326

申请日：2018-09-07

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: G11C11/4091 ,  G11C11/56 ,  G11C11/4094

Abstract: An electronic device includes: a memory cell configured to store electric charge for representing a data value, wherein the memory cell is configured to store two or more levels of the electric charge corresponding to different data values; a preamplifier operably coupled to the memory cell, the preamplifier having a common source and configured to generate an amplified signal based on amplifying a difference in the two or more levels of the stored electric charge; and a sense amplifier operably coupled to the preamplifier, the sense amplifier configured to further process the amplified signal for determining the data value stored in the memory cell.