公开(公告)号：US20240248619A1

公开(公告)日：2024-07-25

申请号：US18406687

申请日：2024-01-08

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung LIEN ,  Zhenming ZHOU ,  Tomer Tzvi ELIASH

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and apparatuses include determining to apply a read retry operation to a portion of memory. The likelihood of a read retry timeout meeting a threshold is determined. A reverse trim setting is selected in response to determining the likelihood of the read retry timeout meets the threshold. The read retry operation is executed using the selected trim setting.

公开(公告)号：US20240420783A1

公开(公告)日：2024-12-19

申请号：US18820480

申请日：2024-08-30

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung LIEN ,  Zhenming ZHOU ,  Tomer Tzvi ELIASH

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/24 ,  G11C16/32

Abstract: Implementations described herein relate to detecting a memory write reliability risk without using a write verify operation. In some implementations, a memory device may perform a program operation that includes a single program pulse and that does not include a program verify operation immediately after the single program pulse. The memory device may set a flag value based on comparing a transition time and a transition time threshold. The transition time may be a time to transition from a first voltage to a second voltage during the program operation. The memory device may selectively perform a mitigation operation based on whether the flag value is set to a first value or a second value.

公开(公告)号：US20240055060A1

公开(公告)日：2024-02-15

申请号：US17819826

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung LIEN ,  Zhenming ZHOU ,  Tomer Tzvi ELIASH

IPC: G11C16/34 ,  G11C16/32 ,  G11C16/10 ,  G11C16/24

CPC classification number: G11C16/3459 ,  G11C16/32 ,  G11C16/102 ,  G11C16/24

Abstract: Implementations described herein relate to detecting a memory write reliability risk without using a write verify operation. In some implementations, a memory device may perform a program operation that includes a single program pulse and that does not include a program verify operation immediately after the single program pulse. The memory device may set a flag value based on comparing a transition time and a transition time threshold. The transition time may be a time to transition from a first voltage to a second voltage during the program operation. The memory device may selectively perform a mitigation operation based on whether the flag value is set to a first value or a second value.