公开(公告)号：US20240289218A1

公开(公告)日：2024-08-29

申请号：US18586048

申请日：2024-02-23

Applicant: Micron Technology, Inc.

Inventor： David Ebsen ,  Kishore Kumar Muchherla ,  James Fitzpatrick ,  Dung V. Nguyen ,  Kevin R. Brandt ,  Vikas Rana ,  William Richard Akin

IPC: G06F11/10 ,  G06F13/16

CPC classification number: G06F11/1068 ,  G06F11/1004 ,  G06F13/1673

Abstract: Data is read from a set of memory cells of a memory device to a buffer of the memory device. One or more bits in error in the data stored by the buffer are corrected by a decoder of the memory device. The decoder corrects the one or more bits in error by decoding the data stored by the buffer. The decoding of the data results in corrected data. An encoder of the memory device encodes the corrected data and the encoded corrected data is programmed to the set of memory cells.

公开(公告)号：US12067253B2

公开(公告)日：2024-08-20

申请号：US17666087

申请日：2022-02-07

Applicant: Micron Technology, Inc.

Inventor： Karl D. Schuh ,  William Richard Akin

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679

Abstract: Exemplary methods, apparatuses, and systems include determining that a memory component to be subjected to a background data integrity scan does not currently satisfy an activity threshold. The background data integrity scan is delayed in response to determining memory component does not satisfy the activity threshold. In response to detecting a background data integrity scan trigger event, the background data integrity scan is performed.

公开(公告)号：US20240379153A1

公开(公告)日：2024-11-14

申请号：US18781804

申请日：2024-07-23

Applicant: Micron Technology, Inc.

Inventor： Karl D. Schuh ,  William Richard Akin

IPC: G11C11/4093 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4096

Abstract: Exemplary methods, apparatuses, and systems include allotting an initial amount of volatile memory to a write buffer. The write buffer stores batches of data to be written to non-volatile memory. In response to detecting a trigger to update the write buffer configuration, the volatile memory allotted to the write buffer is reduced.

公开(公告)号：US20230064781A1

公开(公告)日：2023-03-02

申请号：US17462870

申请日：2021-08-31

Applicant: Micron Technology, Inc.

Inventor： Karl D. Schuh ,  William Richard Akin

IPC: G11C11/4093 ,  G11C11/4096 ,  G11C11/4076 ,  G11C11/4074

Abstract: Exemplary methods, apparatuses, and systems include allotting an initial amount of volatile memory to a write buffer. The write buffer stores batches of data to be written to non-volatile memory. In response to detecting a trigger to update the write buffer configuration, the volatile memory allotted to the write buffer is reduced.

公开(公告)号：US20240012713A1

公开(公告)日：2024-01-11

申请号：US18474046

申请日：2023-09-25

Applicant: Micron Technology, Inc.

Inventor： Joseph Harold Steinmetz ,  William Richard Akin

IPC: G06F11/14

CPC classification number: G06F11/1415 ,  G06F2201/805

Abstract: Exemplary methods, apparatuses, and systems include detecting a failure of a first memory subsystem of a plurality of memory subsystems. A first recovery instruction is sent to a second memory subsystem of the plurality of memory subsystems. The first recovery instruction directs the second memory subsystem to recover a first subset of data stored by the first memory subsystem. A second recovery instruction is sent to a third memory subsystem of the plurality of memory subsystems. The second recovery instruction directs the third memory subsystem to rebuild a second subset of data stored by the first memory subsystem. The first and second subsets of data differ from one another.

公开(公告)号：US11803444B1

公开(公告)日：2023-10-31

申请号：US17841106

申请日：2022-06-15

Applicant: Micron Technology, Inc.

Inventor： Joseph Harold Steinmetz ,  William Richard Akin

IPC: G06F11/14

CPC classification number: G06F11/1415 ,  G06F2201/805

Abstract: Exemplary methods, apparatuses, and systems include detecting a failure of a first memory subsystem of a plurality of memory subsystems. A first recovery instruction is sent to a second memory subsystem of the plurality of memory subsystems. The first recovery instruction directs the second memory subsystem to recover a first subset of data stored by the first memory subsystem. A second recovery instruction is sent to a third memory subsystem of the plurality of memory subsystems. The second recovery instruction directs the third memory subsystem to rebuild a second subset of data stored by the first memory subsystem. The first and second subsets of data differ from one another.

公开(公告)号：US12111731B2

公开(公告)日：2024-10-08

申请号：US18474046

申请日：2023-09-25

Applicant: Micron Technology, Inc.

Inventor： Joseph Harold Steinmetz ,  William Richard Akin

IPC: G06F11/14

CPC classification number: G06F11/1415 ,  G06F2201/805

Abstract: Exemplary methods, apparatuses, and systems include detecting a failure of a first memory subsystem of a plurality of memory subsystems. A first recovery instruction is sent to a second memory subsystem of the plurality of memory subsystems. The first recovery instruction directs the second memory subsystem to recover a first subset of data stored by the first memory subsystem. A second recovery instruction is sent to a third memory subsystem of the plurality of memory subsystems. The second recovery instruction directs the third memory subsystem to rebuild a second subset of data stored by the first memory subsystem. The first and second subsets of data differ from one another.

公开(公告)号：US12073873B2

公开(公告)日：2024-08-27

申请号：US17462870

申请日：2021-08-31

Applicant: Micron Technology, Inc.

Inventor： Karl D. Schuh ,  William Richard Akin

IPC: G11C7/10 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4096

Abstract: Exemplary methods, apparatuses, and systems include allotting an initial amount of volatile memory to a write buffer. The write buffer stores batches of data to be written to non-volatile memory. In response to detecting a trigger to update the write buffer configuration, the volatile memory allotted to the write buffer is reduced.

公开(公告)号：US20230251779A1

公开(公告)日：2023-08-10

申请号：US17666087

申请日：2022-02-07

Applicant: Micron Technology, Inc.

Inventor： Karl D. Schuh ,  William Richard Akin

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679

Abstract: Exemplary methods, apparatuses, and systems include determining that a memory component to be subjected to a background data integrity scan does not currently satisfy an activity threshold. The background data integrity scan is delayed in response to determining memory component does not satisfy the activity threshold. In response to detecting a background data integrity scan trigger event, the background data integrity scan is performed.