公开(公告)号：US20170256529A1

公开(公告)日：2017-09-07

申请号：US15063117

申请日：2016-03-07

申请人： Micron Technology, Inc.

发明人： Yasuhiko Tanuma ,  Takashi Ishihara

IPC分类号： H01L27/02 ,  G06F17/50 ,  H01L27/06

CPC分类号： H01L27/0207 ,  G06F17/5072 ,  H01L27/0629 ,  H01L27/11807

摘要： Apparatuses including circuit layout regions of a semiconductor device and methods of designing the circuit layout regions of a semiconductor device are described. An example apparatus includes a first layout region including a first transistor area including at least one first transistor, at least one contact in proximity to the first transistor area, and a first resistor area comprising at least one first resistor coupled to the at least one first transistor. The first transistor area and the at least one contact are aligned in a first direction, and the first transistor area and the first resistor area are aligned in a second direction. The second direction may be substantially perpendicular to the first direction. The at least one contact may be one of a substrate contact and a well contact.

公开(公告)号：US10811059B1

公开(公告)日：2020-10-20

申请号：US16366100

申请日：2019-03-27

申请人： Micron Technology, Inc.

发明人： Takayori Hamada ,  Yasuhiko Tanuma

IPC分类号： G11C5/06 ,  G11C7/10 ,  H01L23/522

摘要： Semiconductor devices and systems include semiconductor devices with first signal traces conveying a first power signal, second signal traces conveying a second power signal, and third signal traces conveying a third power signal. Each of the power signals are connected on a redistribution layer, a first wiring layer, and first-layer contacts. At least one of the first signal traces on the redistribution layer includes a cutout region and the third signal traces include a bypass structure on the redistribution layer and within the cutout region. The bypass structure conveys the third power signal on the redistribution layer around the first-layer contacts coupled to the first signal traces on the redistribution layer.

公开(公告)号：US10332873B2

公开(公告)日：2019-06-25

申请号：US15619811

申请日：2017-06-12

申请人： Micron Technology, Inc.

发明人： Toshinao Ishii ,  Yasuhiko Tanuma

IPC分类号： H01L23/525 ,  H01L27/06

摘要： An apparatus comprises an antifuse cell comprising first and second nodes, an antifuse element, and a transistor. The antifuse element and the transistor are coupled in series between the first and second nodes. The antifuse element comprises an antifuse gate. The transistor comprises a transistor gate comprising a substantially-annular structure substantially surrounding the antifuse gate.

公开(公告)号：US20200321034A1

公开(公告)日：2020-10-08

申请号：US16909677

申请日：2020-06-23

申请人： Micron Technology, Inc.

发明人： Takayori Hamada ,  Yasuhiko Tanuma

IPC分类号： G11C5/06 ,  G11C7/10 ,  H01L23/522

摘要： Semiconductor devices and systems are disclosed. A semiconductor device includes a redistribution layer including a first polygonal structure for conveying a first power signal and including a first cutout region. The semiconductor device further includes a second polygonal structure for conveying a second power signal. Further, the semiconductor device includes an island polygon for conveying a third power signal and positioned within the first cutout region, wherein the island polygon does not touch the first polygonal structure.

公开(公告)号：US20190267368A1

公开(公告)日：2019-08-29

申请号：US16406274

申请日：2019-05-08

申请人： Micron Technology, Inc.

发明人： Toshinao Ishii ,  Yasuhiko Tanuma

IPC分类号： H01L27/06 ,  H01L27/07 ,  H01L23/525

摘要： An apparatus comprises an antifuse cell comprising first and second nodes, an antifuse element, and a transistor. The antifuse element and the transistor are coupled in series between the first and second nodes. The antifuse element comprises an antifuse gate. The transistor comprises a transistor gate comprising a substantially-annular structure substantially surrounding the antifuse gate.

公开(公告)号：US10367053B2

公开(公告)日：2019-07-30

申请号：US15896491

申请日：2018-02-14

申请人： Micron Technology, Inc.

发明人： Yasuhiko Tanuma ,  Takashi Ishihara

IPC分类号： H01L49/02 ,  H01L27/02 ,  H01L27/06 ,  G06F17/50 ,  H01L29/73 ,  H01L27/118

摘要： Apparatuses including circuit layout regions of a semiconductor device and methods of designing the circuit layout regions of a semiconductor device are described. An example apparatus includes a first layout region including a first transistor area including at least one first transistor, at least one contact in proximity to the first transistor area, and a first resistor area comprising at least one first resistor coupled to the at least one first transistor. The first transistor area and the at least one contact are aligned in a first direction, and the first transistor area and the first resistor area are aligned in a second direction. The second direction may be substantially perpendicular to the first direction. The at least one contact may be one of a substrate contact and a well contact.

公开(公告)号：US20180175017A1

公开(公告)日：2018-06-21

申请号：US15896491

申请日：2018-02-14

申请人： Micron Technology, Inc.

发明人： Yasuhiko Tanuma ,  Takashi Ishihara

IPC分类号： H01L27/02 ,  G06F17/50 ,  H01L27/06

CPC分类号： H01L28/20 ,  G06F17/5072 ,  H01L27/0207 ,  H01L27/0288 ,  H01L27/0629 ,  H01L27/11807 ,  H01L28/00 ,  H01L29/7304

摘要： Apparatuses including circuit layout regions of a semiconductor device and methods of designing the circuit layout regions of a semiconductor device are described. An example apparatus includes a first layout region including a first transistor area including at least one first transistor, at least one contact in proximity to the first transistor area, and a first resistor area comprising at least one first resistor coupled to the at least one first transistor. The first transistor area and the at least one contact are aligned in a first direction, and the first transistor area and the first resistor area are aligned in a second direction. The second direction may be substantially perpendicular to the first direction. The at least one contact may be one of a substrate contact and a well contact.

公开(公告)号：US11244942B2

公开(公告)日：2022-02-08

申请号：US16406274

申请日：2019-05-08

申请人： Micron Technology, Inc.

发明人： Toshinao Ishii ,  Yasuhiko Tanuma

IPC分类号： H01L23/525 ,  H01L27/06 ,  H01L27/07

摘要： An apparatus comprises an antifuse cell comprising first and second nodes, an antifuse element, and a transistor. The antifuse element and the transistor are coupled in series between the first and second nodes. The antifuse element comprises an antifuse gate. The transistor comprises a transistor gate comprising a substantially-annular structure substantially surrounding the antifuse gate.

公开(公告)号：US11176970B2

公开(公告)日：2021-11-16

申请号：US16909677

申请日：2020-06-23

申请人： Micron Technology, Inc.

发明人： Takayori Hamada ,  Yasuhiko Tanuma

IPC分类号： G11C5/06 ,  H01L23/522 ,  G11C7/10

摘要： Semiconductor devices and systems are disclosed. A semiconductor device includes a redistribution layer including a first polygonal structure for conveying a first power signal and including a first cutout region. The semiconductor device further includes a second polygonal structure for conveying a second power signal. Further, the semiconductor device includes an island polygon for conveying a third power signal and positioned within the first cutout region, wherein the island polygon does not touch the first polygonal structure.

公开(公告)号：US11101265B2

公开(公告)日：2021-08-24

申请号：US16521800

申请日：2019-07-25

申请人： Micron Technology, Inc.

发明人： Yasuhiko Tanuma ,  Takashi Ishihara

IPC分类号： H01L27/06 ,  H01L27/02 ,  H01L49/02 ,  H01L29/73 ,  H01L27/118 ,  G06F30/392

摘要： Apparatuses including circuit layout regions of a semiconductor device and methods of designing the circuit layout regions of a semiconductor device are described. An example apparatus includes a first layout region including a first transistor area including at least one first transistor, at least one contact in proximity to the first transistor area, and a first resistor area comprising at least one first resistor coupled to the at least one first transistor. The first transistor area and the at least one contact are aligned in a first direction, and the first transistor area and the first resistor area are aligned in a second direction. The second direction may be substantially perpendicular to the first direction. The at least one contact may be one of a substrate contact and a well contact.